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1. 发明授权

US09317288B2 Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline 有权
标题翻译：执行x86 ISA和ARM ISA机器语言程序指令的多核微处理器通过硬件转换为由通用执行管道执行的微指令
公开(公告)号：US09317288B2
公开(公告)日：2016-04-19
申请号：US13412904
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/30 , G06F9/44
CPC分类号： G06F9/30174 , G06F9/30025 , G06F9/30076 , G06F9/30101 , G06F9/30123 , G06F9/3017 , G06F9/30189 , G06F9/4401
摘要： A microprocessor includes a plurality of processing cores each including a hardware instruction translator that translates instructions of x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs into microinstructions defined by a microinstruction set of the microprocessor. The microinstructions are encoded in a distinct manner from the manner in which the instructions of the x86 and ARM instruction sets are defined. Each core includes an execution pipeline that executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. Each core uses and associated indicator to determine whether it will boot as an x86 ISA core or an ARM ISA core when reset. The indicators are configurable to indicate that at least one of the cores will boot as an x86 ISA core and at least one other of the cores will boot as an ARM ISA core.
摘要翻译：微处理器包括多个处理核心，每个处理核心包括将x86指令集架构（ISA）机器语言程序和高级RISC机器（ARM）ISA机器语言程序的指令转换成由微处理器的微指令集定义的微指令的硬件指令转换器。微指令以与定义x86和ARM指令集的指令的方式不同的方式进行编码。每个内核都包含一个执行管道，执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。每个核心使用和相关联的指示器来确定在重置时是否将引导为x86 ISA内核或ARM ISA内核。这些指示符是可配置的，表示至少有一个内核将作为x86 ISA内核引导，并且至少另外一个内核将作为ARM ISA内核引导。

2. 发明授权

US09043580B2 Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA) 有权
标题翻译：对不同指令集架构（ISA）的指令访问具有不同组的不同微指令的模型特定寄存器（MSR）
公开(公告)号：US09043580B2
公开(公告)日：2015-05-26
申请号：US13413346
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/30
CPC分类号： G06F9/30174 , G06F9/30076 , G06F9/30101 , G06F9/30112 , G06F9/3017 , G06F9/30189 , G06F9/30196
摘要： A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.
摘要翻译：能够运行x86指令集架构（ISA）机器语言程序和高级RISC机（ARM）ISA机器语言程序的微处理器。微处理器包括指示微处理器当前是否正在获取x86 ISA或ARM ISA机器语言程序的指令的模式指示器。微处理器还包括多个模型专用寄存器（MSR），其控制微处理器操作的方面。当模式指示符指示微处理器当前正在获取x86 ISA机器语言程序指令时，可通过指定MSR的地址的x86 ISA RDMSR / WRMSR指令访问多个MSR中的每一个。当模式指示符指示微处理器当前正在获取ARM ISA机器语言程序指令时，可通过指定MSR的地址的ARM ISA MRRC / MCRR指令访问多个MSR中的每一个。

3. 发明申请

US20140122847A1 MICROPROCESSOR THAT TRANSLATES CONDITIONAL LOAD/STORE INSTRUCTIONS INTO VARIABLE NUMBER OF MICROINSTRUCTIONS 有权
标题翻译：将条件负载/存储指令转换成可变数量的微处理器的微处理器
公开(公告)号：US20140122847A1
公开(公告)日：2014-05-01
申请号：US14007116
申请日：2012-04-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
IPC分类号： G06F9/26
CPC分类号： G06F9/441 , G06F9/265 , G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/30105 , G06F9/30123 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/3802 , G06F9/4401 , G06F9/4403 , G06F15/82
摘要： An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.
摘要翻译：指令转换器接收指定条件，目标/数据寄存器，基址寄存器，偏移源和存储器寻址模式的条件加载/存储指令。只有当条件标志满足条件时，指令才指示微处理器将数据从存储单元加载到目标寄存器（条件加载）中，或者将数据从数据寄存器（条件存储）存储到存储单元。偏移源指定偏移量是立即值还是偏移量寄存器中的值。寻址模式指定条件标志满足条件时是否更新基址寄存器。指令翻译器将条件加载指令转换为多个微指令，其作为偏移源，寻址模式以及条件指令是条件加载还是存储指令的函数而变化。无序执行流水线执行微指令以生成指令指定的结果。

4. 发明申请

US20130067199A1 CONTROL REGISTER MAPPING IN HETEROGENEOUS INSTRUCTION SET ARCHITECTURE PROCESSOR 有权
标题翻译：异构指令集建筑处理器中的控制寄存器映射
公开(公告)号：US20130067199A1
公开(公告)日：2013-03-14
申请号：US13413346
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/318
CPC分类号： G06F9/30174 , G06F9/30076 , G06F9/30101 , G06F9/30112 , G06F9/3017 , G06F9/30189 , G06F9/30196
摘要： A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.
摘要翻译：能够运行x86指令集架构（ISA）机器语言程序和高级RISC机（ARM）ISA机器语言程序的微处理器。微处理器包括指示微处理器当前是否正在获取x86 ISA或ARM ISA机器语言程序的指令的模式指示器。微处理器还包括多个模型专用寄存器（MSR），其控制微处理器操作的方面。当模式指示符指示微处理器当前正在获取x86 ISA机器语言程序指令时，可通过指定MSR的地址的x86 ISA RDMSR / WRMSR指令访问多个MSR中的每一个。当模式指示符指示微处理器当前正在获取ARM ISA机器语言程序指令时，可通过指定MSR的地址的ARM ISA MRRC / MCRR指令访问多个MSR中的每一个。

5. 发明申请

US20120260074A1 EFFICIENT CONDITIONAL ALU INSTRUCTION IN READ-PORT LIMITED REGISTER FILE MICROPROCESSOR 有权
标题翻译： READ-PORT有限公司注册文件微处理器的有效条件
公开(公告)号：US20120260074A1
公开(公告)日：2012-10-11
申请号：US13333520
申请日：2011-12-21
申请人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/312 , G06F9/315 , G06F9/345 , G06F9/38
CPC分类号： G06F9/30189 , G06F9/30072 , G06F9/30094 , G06F9/30141 , G06F9/30174
摘要： A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result. To execute the second microinstruction, it writes the destination register with the result generated by the first microinstruction if the architectural condition flags satisfy the condition, and writes the destination register with the current value of the destination register if the architectural condition flags do not satisfy the condition.
摘要翻译：一种微处理器，其执行结构指令，指示其在第一和第二源操作数上执行操作以产生结果，并且仅当其结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。硬件指令转换器将指令转换为第一和第二微指令。要执行第一个微指令，执行流水线对源操作数执行操作以生成结果。要执行第二个微指令，如果架构条件标志满足条件，则将目标寄存器写入由第一微指令生成的结果，如果结构条件标志不满足条件标志，则将目标寄存器写入目标寄存器的当前值条件。

6. 发明申请

US20120260067A1 MICROPROCESSOR THAT PERFORMS X86 ISA AND ARM ISA MACHINE LANGUAGE PROGRAM INSTRUCTIONS BY HARDWARE TRANSLATION INTO MICROINSTRUCTIONS EXECUTED BY COMMON EXECUTION PIPELINE 有权
标题翻译：执行X86 ISA和ARM ISA机器语言程序指令的微处理器由硬件翻译成由通用执行管线执行的微指令
公开(公告)号：US20120260067A1
公开(公告)日：2012-10-11
申请号：US13224310
申请日：2011-09-01
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/30
CPC分类号： G06F9/441 , G06F9/265 , G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/30105 , G06F9/30123 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/3802 , G06F9/4401 , G06F9/4403 , G06F15/82
摘要： A microprocessor includes a hardware instruction translator that translates x86 ISA and ARM ISA machine language program instructions into microinstructions, which are encoded in a distinct manner from the x86 and ARM instructions. An execution pipeline executes the microinstructions to generate x86/ARM-defined results. The microinstructions are distinct from the results generated by the execution of the microinstructions by the execution pipeline. The translator directly provides the microinstructions to the execution pipeline for execution. Each time the microprocessor performs one of the x86 ISA and ARM ISA instructions, the translator translates it into the microinstructions. An indicator indicates either x86 or ARM as a boot ISA. After reset, the microprocessor initializes its architectural state, fetches its first instructions from a reset address, and translates them all as defined by the boot ISA. An instruction cache caches the x86 and ARM instructions and provides them to the translator.
摘要翻译：微处理器包括硬件指令转换器，将x86 ISA和ARM ISA机器语言程序指令转换为微指令，它们以不同于x86和ARM指令的方式进行编码。执行流水线执行微指令以生成x86 / ARM定义的结果。微指令与由执行管道执行微指令生成的结果不同。翻译器直接向执行管道提供微指令以供执行。每当微处理器执行x86 ISA和ARM ISA指令之一时，翻译器将其转换为微指令。指示符指示x86或ARM作为引导ISA。复位后，微处理器初始化其架构状态，从复位地址获取其第一条指令，并按照引导ISA定义将其全部转换。指令缓存缓存x86和ARM指令，并将其提供给翻译器。

7. 发明申请

US20120260066A1 HETEROGENEOUS ISA MICROPROCESSOR THAT PRESERVES NON-ISA-SPECIFIC CONFIGURATION STATE WHEN RESET TO DIFFERENT ISA 有权
标题翻译：异步ISA微处理器，当复位到不同的ISA时，保持非特定的配置状态
公开(公告)号：US20120260066A1
公开(公告)日：2012-10-11
申请号：US13412914
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/30174 , G06F9/3017 , G06F9/30181 , G06F9/30189 , G06F9/3844 , G06F9/461
摘要： A microprocessor capable of operating as both an x86 ISA and an ARM ISA microprocessor includes first, second, and third storage that stores x86 ISA-specific, ARM ISA-specific, and non-ISA-specific state, respectively. When reset, the microprocessor initializes the first storage to default values specified by the x86 ISA, initializes the second storage to default values specified by the ARM ISA, initializes the third storage to predetermined values, and begins fetching instructions of a first ISA. The first ISA is the x86 ISA or the ARM ISA and a second ISA is the other ISA. The microprocessor updates the third storage in response to the first ISA instructions. In response to a subsequent one of the first ISA instructions that instructs the microprocessor to reset to the second ISA, the microprocessor refrains from modifying the non-ISA-specific state stored in the third storage and begins fetching instructions of the second ISA.
摘要翻译：能够同时运行x86 ISA和ARM ISA微处理器的微处理器分别包含第一，第二和第三存储，它们分别存储特定于x86 ISA特定的ISA特定状态和非ISA特定状态。当复位时，微处理器将第一个存储器初始化为由x86 ISA指定的默认值，将第二个存储初始化为由ARM ISA指定的默认值，将第三个存储初始化为预定值，并开始获取第一个ISA的指令。第一个ISA是x86 ISA或ARM ISA，另一个ISA是另一个ISA。微处理器响应于第一ISA指令更新第三存储器。响应于指示微处理器重置到第二ISA的第一ISA指令中的随后的一个，微处理器不修改存储在第三存储器中的非ISA特定状态，并开始获取第二ISA的指令。

8. 发明申请

US20110004644A1 DYNAMIC FLOATING POINT REGISTER PRECISION CONTROL 审中-公开
标题翻译：动态浮点注册精度控制
公开(公告)号：US20110004644A1
公开(公告)日：2011-01-06
申请号：US12497570
申请日：2009-07-03
申请人： G. Glenn Henry , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/302 , G06F7/38
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30192
摘要： Apparatus and methods are provided to perform floating point operations that are adaptive to the precision formats of input operands. The apparatus includes adaptive conversion logic and a tagged register file. The adaptive conversion logic receives the input operands, where each of the input operands is of a corresponding precision. The adaptive conversion logic also records the corresponding precision for use in subsequent floating point operations. The tagged register file is coupled to the adaptive conversion logic. The tagged register file stores the each of the input operands, and stores the corresponding precision and furthermore associates the corresponding precision with the each of the input operands. The subsequent floating point operations are performed at a precision level according to the corresponding precision.
摘要翻译：提供装置和方法来执行适应于输入操作数的精度格式的浮点运算。该装置包括自适应转换逻辑和标记的寄存器文件。自适应转换逻辑接收输入操作数，其中每个输入操作数具有相应的精度。自适应转换逻辑还记录用于后续浮点运算的相应精度。标记的寄存器文件耦合到自适应转换逻辑。标记的寄存器文件存储每个输入操作数，并存储对应的精度，并且还将相应的精度与每个输入操作数相关联。随后的浮点运算按照相应的精度在精度级进行。

9. 发明申请

US20080256336A1 MICROPROCESSOR WITH PRIVATE MICROCODE RAM 有权
标题翻译：微处理器与私有MICROCODE RAM
公开(公告)号：US20080256336A1
公开(公告)日：2008-10-16
申请号：US12034503
申请日：2008-02-20
申请人： G. Glenn Henry , Colin Eddy , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Colin Eddy , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/3824 , G06F9/26 , G06F9/30043 , G06F9/30101 , G06F9/30112 , G06F9/30123 , G06F9/30138 , G06F9/30174 , G06F9/3826
摘要： A microprocessor includes a private RAM (PRAM), for use by microcode, which is non-user-accessible and within its own distinct address space from the system memory address space. The PRAM is denser and slower than user-accessible registers of the microprocessor macroarchitecture, thereby enabling it to provide significantly more storage for microcode. The microinstruction set includes a microinstruction for loading data from the PRAM into the user-accessible registers, and a microinstruction for storing data from user-accessible registers to the PRAM. The microcode may also use the two microinstructions to load/store between the PRAM and non-user-accessible registers of the microarchitecture. Examples of PRAM uses include: computational temporary storage area; storage of x86 VMX VMCS in response to VMREAD and VMWRITE macroinstructions; instantiation of non-user-accessible storage, such as the x86 SMBASE register; and instantiation of x86 MSRs that tolerate the additional access latency of the PRAM, such as the IA32_SYSENTER_CS MSR.
摘要翻译：微处理器包括专用RAM（PRAM），用于微码，这是非用户可访问的，并且在其自身与系统存储器地址空间不同的地址空间内。 PRAM比微处理器宏构架的用户可访问的寄存器更密集和更慢，从而使其能够为微码提供显着更多的存储。微指令集包括用于将来自PRAM的数据加载到用户可访问寄存器中的微指令，以及用于将来自用户可访问寄存器的数据存储到PRAM的微指令。微代码还可以使用两个微指令来加载/存储在微架构的PRAM和非用户可访问的寄存器之间。 PRAM使用的示例包括：计算临时存储区域; 存储x86 VMX VMCS以响应VMREAD和VMWRITE宏指令; 实例化非用户可访问的存储，如x86 SMBASE寄存器; 以及容忍PRAM的附加访问延迟（例如IA32_SYSENTER_CS MSR）的x86 MSR的实例化。

10. 发明授权

US07380103B2 Apparatus and method for selective control of results write back 有权
标题翻译：用于选择性控制结果的装置和方法回写
公开(公告)号：US07380103B2
公开(公告)日：2008-05-27
申请号：US10144589
申请日：2002-05-09
申请人： G. Glenn Henry , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/30 , G06F9/00
CPC分类号： G06F9/30185 , G06F9/3016 , G06F9/30174 , G06F9/30189
摘要： A microprocessor apparatus and method are provided, for selectively controlling write back of a result. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix precludes write back of the result, where the result is that which is produced by executing an operation prescribed by said extended instruction, and wherein the result would otherwise be written back into a destination register. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within an instruction set for a microprocessor. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and executes the operation to generate the result, and precludes write back of the result.
摘要翻译：提供了一种微处理器装置和方法，用于选择性地控制结果的回写。该装置包括翻译逻辑和扩展执行逻辑。翻译逻辑将扩展指令转换为相应的微指令。扩展指令具有扩展前缀和扩展前缀标记。扩展前缀排除结果的回写，其中结果是通过执行由所述扩展指令规定的操作产生的结果，并且其中结果将被写回目的地寄存器。扩展前缀标记指示扩展前缀，其中扩展前缀标记是用于微处理器的指令集内的另外结构上指定的操作码。扩展执行逻辑耦合到转换逻辑。扩展执行逻辑接收相应的微指令，并执行产生结果的操作，并排除结果的回写。

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