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1. 发明授权

US07174355B2 Random number generator with selectable dual random bit string engines 有权
标题翻译：随机数发生器与可选双随机位串引擎
公开(公告)号：US07174355B2
公开(公告)日：2007-02-06
申请号：US10365601
申请日：2003-02-11
申请人： G. Glenn Henry , James R. Lundberg , Terry Parks
发明人： G. Glenn Henry , James R. Lundberg , Terry Parks
IPC分类号： G06F7/58
CPC分类号： G06F7/58 , G06F9/30003 , G06F9/3004 , G06F9/30087 , G06F11/27
摘要： A microprocessor with multiple random bit generators is disclosed. The multiple random bit generators each generate a stream of random bits. One of the streams of random bits is selected to be used to accumulate into random bytes for provision to application programs. Which of the multiple random bit generator random bit streams is selected is determined by a selection value stored in a control register of the microprocessor. The selection value is programmable by an instruction executed by the microprocessor.
摘要翻译：公开了一种具有多个随机位发生器的微处理器。多个随机比特发生器产生一个随机比特流。选择随机比特流之一用于累加到随机字节中以供应给应用程序。选择多个随机比特生成器随机比特流中的哪一个由存储在微处理器的控制寄存器中的选择值确定。选择值由微处理器执行的指令编程。

2. 发明授权

US08751851B2 Programmable mechanism for synchronous strobe advance 有权
标题翻译：同步选通提前编程机制
公开(公告)号：US08751851B2
公开(公告)日：2014-06-10
申请号：US13165665
申请日：2011-06-21
申请人： Darius D. Gaskins , James R. Lundberg
发明人： Darius D. Gaskins , James R. Lundberg
IPC分类号： G06F1/12
CPC分类号： G06F13/385
摘要： An apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, a core clocks generator, and a synchronous strobe driver. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to advance a synchronous data strobe associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The core clocks generator is coupled to the ratio bus and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.
摘要翻译：一种装置包括联合测试动作组（JTAG）接口，同步总线优化器，核心时钟发生器和同步选通驱动器。 JTAG接口被配置为通过标准JTAG总线接收控制信息，其中控制信息指示用于推进与数据组相关联的同步数据选通的量。同步总线优化器被配置为接收控制信息，并且被配置为开发指示量的比率总线上的值。核心时钟发生器耦合到比率总线，并被配置为使数据选通时钟提前一定量。同步选通驱动器被配置为接收数据选通时钟，并且被配置为采用数据选通时钟来产生同步数据选通，其中同步数据选通在使能时也被提前量。

3. 发明申请

US20120331326A1 APPARATUS AND METHOD FOR ADVANCED SYNCHRONOUS STROBE TRANSMISSION 有权
标题翻译：用于高级同步走带传输的装置和方法
公开(公告)号：US20120331326A1
公开(公告)日：2012-12-27
申请号：US13165650
申请日：2011-06-21
申请人： Darius D. Gaskins , James R. Lundberg
发明人： Darius D. Gaskins , James R. Lundberg
IPC分类号： G06F1/12
CPC分类号： G06F13/423 , H03L7/081
摘要： An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a core clocks generator, and a synchronous strobe driver. The resistor network is configured to provide a ratio signal that indicates an amount to advance a synchronous data strobe associated with a data group. The core clocks generator is coupled to the ratio signal, and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.
摘要翻译：提供了一种补偿同步数据总线上的未对准的装置。该装置包括电阻网络，核心时钟发生器和同步选通驱动器。电阻网络被配置为提供指示用于推进与数据组相关联的同步数据选通的量的比率信号。核心时钟发生器耦合到比率信号，并且被配置为使数据选通时钟提前一定量。同步选通驱动器被配置为接收数据选通时钟，并且被配置为采用数据选通时钟来产生同步数据选通，其中同步数据选通在使能时也被提前量。

4. 发明授权

US07990180B2 Fast dynamic register 有权
标题翻译：快速动态寄存器
公开(公告)号：US07990180B2
公开(公告)日：2011-08-02
申请号：US12555999
申请日：2009-09-09
申请人： James R. Lundberg , Imran Qureshi
发明人： James R. Lundberg , Imran Qureshi
IPC分类号： H03K19/096 , H03K19/00
CPC分类号： H03K19/01728
摘要： A fast dynamic register circuit including first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of a pair of precharge nodes and cooperate to minimize setup and hold times. If an input data node is low when the clock goes high, the first precharge node remains high causing the second precharge node to be discharged. Otherwise if the input node is high, the first precharge node is discharged and the second remains charged. Once either precharge node is discharged, the output state of the register remains fixed until the next rising clock edge independent of changes of the input data node. The fast dynamic register may be implemented with multiple inputs to perform common logic operations, such as OR, NOR, AND and NAND logic operations.
摘要翻译：一种快速动态寄存器电路，包括第一和第二预充电电路，保持器电路和输出电路。第一和第二预充电电路各自预先对一对预充电节点中的一个预充电节点进行充电，并进行协作以最小化建立和保持时间。如果在时钟变高时输入数据节点为低电平，则第一预充电节点保持高电平，从而使第二预充电节点放电。否则，如果输入节点为高电平，则第一个预充电节点放电，第二个保持充电。一旦预充电节点放电，寄存器的输出状态保持固定，直到下一个上升时钟沿独立于输入数据节点的变化。快速动态寄存器可以用多个输入来实现，以执行诸如OR，NOR，AND和NAND逻辑运算之类的公共逻辑运算。

5. 发明授权

US07804923B2 Apparatus and method for locking out a source synchronous strobe receiver 有权
标题翻译：用于锁定源同步选通接收机的装置和方法
公开(公告)号：US07804923B2
公开(公告)日：2010-09-28
申请号：US11687810
申请日：2007-03-19
申请人： James R. Lundberg
发明人： James R. Lundberg
IPC分类号： H04L7/00
CPC分类号： H03L7/0814 , H03L7/0805
摘要： An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and one or more receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector that both indicate a lockout time. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by the lockout time. The lockout time is slightly less than a number of cycles of the reference clock. The one or more receivers are each coupled to the delay-locked loop. Each of the one or more receivers receives the encoded select vector and a corresponding strobe, and locks out reception of the corresponding strobe for the lockout time following transition of the corresponding strobe. The encoded select vector is employed to determine the lockout time by selecting a delayed version of the corresponding strobe.
摘要翻译：一种用于锁定源同步选通接收机的装置，包括延迟锁定环（DLL）和一个或多个接收机。 DLL接收参考时钟，并产生指示锁定时间的选择向量和编码选择向量。选择向量用于选择延迟版本的参考时钟，该参考时钟滞后于参考时钟的锁定时间。锁定时间略小于参考时钟的周期数。一个或多个接收器各自耦合到延迟锁定环。一个或多个接收器中的每个接收器接收编码的选择矢量和相应的选通信号，并锁定对应的选通脉冲的接收，用于对应选通脉冲的转换之后的锁定时间。采用经编码的选择向量，通过选择对应选通脉冲的延迟版本来确定锁定时间。

6. 发明授权

US07543090B2 Double-pumped/quad-pumped variation mechanism for source synchronous strobe lockout 有权
标题翻译：用于源同步选通锁定的双泵/四泵浦变化机构
公开(公告)号：US07543090B2
公开(公告)日：2009-06-02
申请号：US11687899
申请日：2007-03-19
申请人： James R. Lundberg
发明人： James R. Lundberg
IPC分类号： G06F3/00 , H03L7/00 , G06F1/12
CPC分类号： G06F13/4243
摘要： An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by a prescribed number of cycles. The select vector is reduced by an amount and is gray encoded to indicate a first time. The receivers are each coupled to the delay-locked loop. Each of the receivers receives the encoded select vector and a corresponding strobe, and locks out reception of die corresponding strobe for a configurable lockout lime following transition of the corresponding strobe. The encoded select vector is employed by a gray code mux therein to determine the configurable lockout time by selecting a delayed version of the corresponding strobe.
摘要翻译：一种用于锁定源同步选通接收器的装置，包括延迟锁定环（DLL）和接收器。 DLL接收参考时钟，并生成选择向量和编码选择向量。选择向量用于选择滞后参考时钟规定次数的参考时钟的延迟版本。选择矢量减少量，并进行灰度编码以指示第一次。接收器各自耦合到延迟锁定环路。每个接收器接收编码的选择矢量和相应的选通信号，并锁定相应的选通脉冲的转换后可配置的锁定电路的相应选通脉冲的接收。编码的选择矢量由其中的灰度码复用器采用，以通过选择对应的频闪的延迟版本来确定可配置的锁定时间。

7. 发明授权

US07358758B2 Apparatus and method for enabling a multi-processor environment on a bus 有权
标题翻译：在总线上实现多处理器环境的装置和方法
公开(公告)号：US07358758B2
公开(公告)日：2008-04-15
申请号：US11422001
申请日：2006-06-02
申请人： Darius D. Gaskins , James R. Lundberg
发明人： Darius D. Gaskins , James R. Lundberg
IPC分类号： H03K17/16
CPC分类号： G06F13/4086
摘要： The present invention provides a technique for enabling multiple devices to be interfaced together over a bus that requires dynamic impedance controls. In one embodiment, an apparatus is provided for enabling a multi-device environment on a bus, where the bus requires active termination impedance control. The apparatus includes a first node and multi-processor logic. The first node receives an indication that a corresponding device is at a physical end of the bus or that the corresponding device is an internal device. The multi-processor logic is coupled to the first node. The multi-processor logic controls how a second node is driven according to the indication, where the second node is coupled to the bus.
摘要翻译：本发明提供了一种使多个设备能够通过需要动态阻抗控制的总线连接在一起的技术。在一个实施例中，提供了一种用于在总线上实现多设备环境的装置，其中总线需要主动终端阻抗控制。该装置包括第一节点和多处理器逻辑。第一节点接收到相应设备处于总线的物理端的指示，或者对应的设备是内部设备。多处理器逻辑耦合到第一节点。多处理器逻辑控制如何根据第二节点耦合到总线的指示来驱动第二节点。

8. 发明授权

US07187210B2 P-domino register 有权
标题翻译：多米诺骨牌登记册
公开(公告)号：US07187210B2
公开(公告)日：2007-03-06
申请号：US11251384
申请日：2005-10-14
申请人： James R. Lundberg , Raymond A. Bertram
发明人： James R. Lundberg , Raymond A. Bertram
IPC分类号： H03K19/096 , H03K3/356
CPC分类号： H03K19/0963
摘要： A P-domino register includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to a pulsed clock signal, and evaluates a logic function according to the states of at least one data signal and the pulsed clock signal, where the domino stage pre-charges a pre-charged node low when the pulsed clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the pulsed clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the pulsed clock signal is low, where a setup state of the at least one data signal is provided to the domino stage when the pulsed clock signal is high.
摘要翻译：多米诺骨牌寄存器包括多米诺骨牌阶段，写阶段，逆变器，低保持者路径，高守护者路径和输出阶段。多米诺舞台与脉冲时钟信号耦合，并根据至少一个数据信号和脉冲时钟信号的状态评估逻辑功能，其中多米诺舞台预充电节点为低电平时，脉冲时钟信号如果逻辑功能评估脉冲时钟信号为低电平时，将预充电节点放电到高电平状态，并且如果逻辑功能未能评估脉冲时钟信号为低电平时，将预充电节点保持在低电平，其中当脉冲时钟信号为高时，至少一个数据信号的设置状态被提供给多米诺骨牌阶段。

9. 发明授权

US06512405B1 Oscillator bias variation mechanism 有权
标题翻译：振荡器偏置变化机制
公开(公告)号：US06512405B1
公开(公告)日：2003-01-28
申请号：US10046054
申请日：2002-01-14
申请人： James R. Lundberg
发明人： James R. Lundberg
IPC分类号： H03K384
CPC分类号： G06F7/588
摘要： A hardware-based random number generator is provided for incorporation within an integrated circuit. The apparatus has a first variable frequency oscillator, a second variable frequency oscillator, and a variable bias generator. The first variable frequency oscillator generates a first oscillatory signal at a first frequency. The a second variable frequency oscillator generates a second oscillatory signal that is asynchronous to the first oscillatory signal and has a second frequency less than the first frequency, where bits of the random number are configured from samples of the first oscillatory signal taken at the second frequency. The variable bias generator is coupled to the first and second variable frequency oscillators, and generates an analog bias signal. The first and second frequencies vary according to the analog bias signal, and the analog bias signal varies based upon logic states of a plurality of bits of the random number.
摘要翻译：提供了一种基于硬件的随机数发生器用于集成在集成电路中。该装置具有第一可变频率振荡器，第二可变频率振荡器和可变偏置发生器。第一可变频率振荡器以第一频率产生第一振荡信号。第二可变频率振荡器产生与第一振荡信号异步的第二振荡信号，并且具有小于第一频率的第二频率，其中随机数的位由第二频率取得的第一振荡信号的采样构成。可变偏置发生器耦合到第一和第二可变频率振荡器，并产生模拟偏置信号。第一和第二频率根据模拟偏置信号而变化，并且模拟偏置信号基于随机数的多个位的逻辑状态而变化。

10. 发明授权

US06420924B1 Slew-controlled split-voltage output driver 有权
标题翻译：压控分压输出驱动器
公开(公告)号：US06420924B1
公开(公告)日：2002-07-16
申请号：US09150316
申请日：1998-09-09
申请人： James R. Lundberg
发明人： James R. Lundberg
IPC分类号： H03L500
CPC分类号： H03K17/163 , H03K19/0013
摘要： A CMOS slew-controlled split-voltage output driver is provided whose I/O logic is supplied at one (higher) voltage level and whose computational logic is supplied at a second (lower) voltage level. The slew-controlled split-voltage output driver includes an output driver circuit, a driver control circuit, and a feedback-enhanced level translator circuit. The output driver circuit drives the output signal to a low level, a high level, or a tri-state level. The driver control circuit receives an enable signal, and employs the enable signal to control turn on and turn off of the N-channel sink transistor. The feedback-enhanced level translator circuit receives an output state signal whose highlevel state is essentially equal to a second power supply voltage. The feedback-enhanced level translator circuit generates the enable signal to the level essentially equal to the first power supply voltage, and isolates generation of the enable signal from operation of the driver control circuit.
摘要翻译：提供了一种CMOS压摆控制分压输出驱动器，其I / O逻辑以一个（较高）电压电平提供，并且其计算逻辑以第二（较低）电压电平提供。转换控制的分压输出驱动器包括输出驱动器电路，驱动器控制电路和反馈增强电平转换器电路。输出驱动电路将输出信号驱动到低电平，高电平或三态电平。驱动器控制电路接收使能信号，采用使能信号来控制N沟道晶体管的导通和截止。反馈增强电平转换器电路接收高电平状态基本上等于第二电源电压的输出状态信号。反馈增强电平转换器电路将使能信号产生到基本上等于第一电源电压的电平，并且将使能信号的产生与驱动器控制电路的操作隔离开来。

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