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1. 发明授权

US08321489B2 Software reconfigurable digital phase lock loop architecture 有权
标题翻译：软件可重构数字锁相环架构
公开(公告)号：US08321489B2
公开(公告)日：2012-11-27
申请号：US11853575
申请日：2007-09-11
申请人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
发明人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
IPC分类号： G06F17/10
CPC分类号： H03L7/0992 , G06F7/605 , G06F9/30014 , G06F9/30032 , G06F9/30181 , G06F17/10 , H03L7/1974 , H03L7/1976 , H03L2207/50 , H04B1/04 , H04W56/003
摘要： A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
摘要翻译：一种基于软件的锁相环（PLL）的新颖有用的装置和方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）包括其指令被优化以执行PLL的原子操作的指令集。 RCU以足够快的处理器时钟速率提供时钟，以确保所有PLL原子操作在单个PLL参考时钟周期内执行。

2. 发明授权

US08134411B2 Computation spreading utilizing dithering for spur reduction in a digital phase lock loop 有权
标题翻译：计算扩展利用抖动在数字锁相环中进行锐减
公开(公告)号：US08134411B2
公开(公告)日：2012-03-13
申请号：US12104778
申请日：2008-04-17
申请人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
发明人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
IPC分类号： H03L7/06
CPC分类号： H03L1/022
摘要： A novel and useful apparatus for and method of spur reduction using computation spreading with dithering in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over a PLL reference clock period wherein each computation is performed at a much higher processor clock frequency than the PLL reference clock rate. This significantly reduces the per cycle current transient generated by the computations. The frequency content of the current transients is at the higher processor clock frequency which results in a significant reduction in spurs within sensitive portions of the output spectrum. Further reduction in spurs is achieved by dithering the duration of the software loop of atomic operations and/or by randomly shuffling one or more non-data dependent instructions within each iteration of the software loop.
摘要翻译：一种用于数字锁相环（DPLL）架构中使用抖动的计算扩展的杂散减少的新颖有用的装置和方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）适于在PLL参考时钟周期内扩展原子操作的计算，其中每个计算以比PLL参考时钟速率高得多的处理器时钟频率执行。这显着地减少了由计算产生的每个周期的电流瞬变。电流瞬变的频率内容处于更高的处理器时钟频率，这导致输出频谱的敏感部分内的杂散的显着减少。通过对原子操作的软件循环的持续时间进行抖动和/或通过在软件循环的每次迭代内随机混洗一个或多个非依赖于数据的指令来实现毛刺的进一步减少。

3. 发明授权

US07809927B2 Computation parallelization in software reconfigurable all digital phase lock loop 有权
标题翻译：软件中的计算并行化可重构所有数字锁相环
公开(公告)号：US07809927B2
公开(公告)日：2010-10-05
申请号：US11949310
申请日：2007-12-03
申请人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
发明人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30003 , G06F9/30014 , G06F9/30032 , G06F9/30181 , G06F9/345 , G06F9/3875 , G06F9/3885 , G06F9/3897 , H03L7/085 , H03L7/091 , H03L7/1806 , H03L7/1974 , H03L2207/50
摘要： A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. A multi-stage data stream based processor incorporates a parallel/pipelined architecture optimized to perform data stream processing efficiently. The multi-stage parallel/pipelined processor provides significantly higher processing speeds by combining multiple RCUs wherein input data samples are input in parallel to all RCUs while computation results from one RCU are used by adjacent downstream RCUs. A register file provides storage for historical values while local storage in each RCU provides storage for temporary results.
摘要翻译：一种基于软件的锁相环（PLL）的新颖有用的装置和方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）包括其指令被优化以执行PLL的原子操作的指令集。基于多级数据流的处理器集成了经过优化的并行/流水线架构，以有效地执行数据流处理。多级并行/流水线处理器通过组合多个RCU来提供显着更高的处理速度，其中输入数据样本与所有RCU并行输入，而来自一个RCU的计算结果由相邻的下游RCU使用。寄存器文件为历史值提供存储，而每个RCU中的本地存储为临时结果提供存储。

4. 发明申请

US20080069286A1 Computation spreading for spur reduction in a digital phase lock loop 有权
标题翻译：在数字锁相环中用于锐减的计算扩展
公开(公告)号：US20080069286A1
公开(公告)日：2008-03-20
申请号：US11853588
申请日：2007-09-11
申请人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
发明人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
IPC分类号： H03L7/06
CPC分类号： H03L7/1806 , G06F1/04 , H03J1/0008 , H03L7/085 , H03L2207/50
摘要： A novel and useful apparatus for and method of spur reduction using computation spreading in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over and completed within an entire PLL reference clock period. Each computation being performed at a much higher processor clock frequency than the PLL reference clock rate. This functions to significantly reduce the per cycle current transient generated by the computations. Further, the frequency content of the current transients is at the higher processor clock frequency. This results in a significant reduction in spurs within sensitive portions of the output spectrum.
摘要翻译：一种新颖有用的装置和使用数字锁相环（DPLL）架构中的计算扩展的杂散减少方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）适于将原子操作的计算扩展到整个PLL参考时钟周期内并在整个PLL参考时钟周期内完成。每个计算以比PLL参考时钟速率高得多的处理器时钟频率执行。这个功能可以显着地减少由计算产生的每个周期的电流瞬变。此外，电流瞬变的频率内容处于较高的处理器时钟频率。这导致在输出光谱的敏感部分内杂散的显着减少。

5. 发明授权

US07936221B2 Computation spreading for spur reduction in a digital phase lock loop 有权
标题翻译：在数字锁相环中用于锐减的计算扩展
公开(公告)号：US07936221B2
公开(公告)日：2011-05-03
申请号：US11853588
申请日：2007-09-11
申请人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
发明人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
IPC分类号： H03L7/06
CPC分类号： H03L7/1806 , G06F1/04 , H03J1/0008 , H03L7/085 , H03L2207/50
摘要： A novel and useful apparatus for and method of spur reduction using computation spreading in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over and completed within an entire PLL reference clock period. Each computation being performed at a much higher processor clock frequency than the PLL reference clock rate. This functions to significantly reduce the per cycle current transient generated by the computations. Further, the frequency content of the current transients is at the higher processor clock frequency. This results in a significant reduction in spurs within sensitive portions of the output spectrum.
摘要翻译：一种新颖有用的装置和使用数字锁相环（DPLL）架构中的计算扩展的杂散减少方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）适于将原子操作的计算扩展到整个PLL参考时钟周期内并在整个PLL参考时钟周期内完成。每个计算以比PLL参考时钟速率高得多的处理器时钟频率执行。这个功能可以显着地减少由计算产生的每个周期的电流瞬变。此外，电流瞬变的频率内容处于较高的处理器时钟频率。这导致在输出光谱的敏感部分内杂散的显着减少。

6. 发明申请

US20090070568A1 Computation parallelization in software reconfigurable all digital phase lock loop 有权
标题翻译：软件中的计算并行化可重构所有数字锁相环
公开(公告)号：US20090070568A1
公开(公告)日：2009-03-12
申请号：US11949310
申请日：2007-12-03
申请人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
发明人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
IPC分类号： G06F9/38
CPC分类号： G06F9/3004 , G06F9/30003 , G06F9/30014 , G06F9/30032 , G06F9/30181 , G06F9/345 , G06F9/3875 , G06F9/3885 , G06F9/3897 , H03L7/085 , H03L7/091 , H03L7/1806 , H03L7/1974 , H03L2207/50
摘要： A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. A multi-stage data stream based processor incorporates a parallel/pipelined architecture optimized to perform data stream processing efficiently. The multi-stage parallel/pipelined processor provides significantly higher processing speeds by combining multiple RCUs wherein input data samples are input in parallel to all RCUs while computation results from one RCU are used by adjacent downstream RCUs. A register file provides storage for historical values while local storage in each RCU provides storage for temporary results.
摘要翻译：一种基于软件的锁相环（PLL）的新颖有用的装置和方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）包括其指令被优化以执行PLL的原子操作的指令集。基于多级数据流的处理器集成了经过优化的并行/流水线架构，以有效地执行数据流处理。多级并行/流水线处理器通过组合多个RCU来提供显着更高的处理速度，其中输入数据样本与所有RCU并行输入，而来自一个RCU的计算结果由相邻的下游RCU使用。寄存器文件为历史值提供存储，而每个RCU中的本地存储为临时结果提供存储。

7. 发明申请

US20080072025A1 Software reconfigurable digital phase lock loop architecture 有权
标题翻译：软件可重构数字锁相环架构
公开(公告)号：US20080072025A1
公开(公告)日：2008-03-20
申请号：US11853575
申请日：2007-09-11
申请人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
发明人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
IPC分类号： G06F9/302 , G06F9/44
CPC分类号： H03L7/0992 , G06F7/605 , G06F9/30014 , G06F9/30032 , G06F9/30181 , G06F17/10 , H03L7/1974 , H03L7/1976 , H03L2207/50 , H04B1/04 , H04W56/003
摘要： A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
摘要翻译：一种基于软件的锁相环（PLL）的新颖有用的装置和方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）包括其指令被优化以执行PLL的原子操作的指令集。 RCU以足够快的处理器时钟速率提供时钟，以确保所有PLL原子操作在单个PLL参考时钟周期内执行。

8. 发明申请

US20090262877A1 Computation spreading utilizing dithering for spur reduction in a digital phase lock loop 有权
标题翻译：计算扩展利用抖动在数字锁相环中进行锐减
公开(公告)号：US20090262877A1
公开(公告)日：2009-10-22
申请号：US12104778
申请日：2008-04-17
申请人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
发明人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
IPC分类号： H03L7/06 , G06F9/44
CPC分类号： H03L1/022
摘要： A novel and useful apparatus for and method of spur reduction using computation spreading with dithering in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over a PLL reference clock period wherein each computation is performed at a much higher processor clock frequency than the PLL reference clock rate. This significantly reduces the per cycle current transient generated by the computations. The frequency content of the current transients is at the higher processor clock frequency which results in a significant reduction in spurs within sensitive portions of the output spectrum. Further reduction in spurs is achieved by dithering the duration of the software loop of atomic operations and/or by randomly shuffling one or more non-data dependent instructions within each iteration of the software loop.
摘要翻译：一种用于数字锁相环（DPLL）架构中使用抖动的计算扩展的杂散减少的新颖有用的装置和方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）适于在PLL参考时钟周期内扩展原子操作的计算，其中每个计算以比PLL参考时钟速率高得多的处理器时钟频率执行。这显着地减少了由计算产生的每个周期的电流瞬变。电流瞬变的频率内容处于更高的处理器时钟频率，这导致输出频谱的敏感部分内的杂散的显着减少。通过对原子操作的软件循环的持续时间进行抖动和/或通过在软件循环的每次迭代内随机混洗一个或多个非依赖于数据的指令来实现毛刺的进一步减少。

9. 发明申请

US20110261871A1 ALL-DIGITAL FREQUENCY SYNTHESIS WITH DCO GAIN CALCULATION 有权
标题翻译：全数字频率合成与DCO增益计算
公开(公告)号：US20110261871A1
公开(公告)日：2011-10-27
申请号：US13175594
申请日：2011-07-01
申请人： Robert B. Staszewski , Dirk Leipold , John Wallberg
发明人： Robert B. Staszewski , Dirk Leipold , John Wallberg
IPC分类号： H04B17/00
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (Δfmax) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator.
摘要翻译：全数字频率合成器架构围绕数字控制振荡器（DCO）构建，该振荡器响应于数字调谐字（OTW）进行调谐。在示例性实施例中：（1）数字控制振荡器的增益特性（KDCO）可以通过在振荡频率中的已知变化（＆Dgr; fmax）之前和之后观察数字控制字来确定; 和（2）调谐字的一部分（TUNE_TF）可以被抖动（1202），并且所得到的抖动部分（dkTF）然后可以被施加到数字控制振荡器内的可切换装置的控制输入。

10. 发明授权

US08027657B2 Sampling mixer with asynchronous clock and signal domains 有权
标题翻译：具有异步时钟和信号域的采样混频器
公开(公告)号：US08027657B2
公开(公告)日：2011-09-27
申请号：US10121761
申请日：2002-04-12
申请人： Robert B. Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
IPC分类号： H04B1/26 , H04L27/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.
摘要翻译：具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。利用混频器中不同采样电容器之间的显着电容差和叠加特性。

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