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1. 发明授权

US08395412B2 Calibration circuit, semiconductor device including the same, and data processing system 有权
标题翻译：校准电路，包括相同的半导体器件和数据处理系统
公开(公告)号：US08395412B2
公开(公告)日：2013-03-12
申请号：US13067644
申请日：2011-06-16
申请人： Fumiyuki Osanai , Hiroki Fujisawa
发明人： Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H03K17/16
CPC分类号： H03K19/0005
摘要： A method includes issuing a calibration command and performing a calibration operation in response to the calibration command. The calibration operation includes adjusting an impedance of a first replica buffer with updating a first code, the first replica buffer being substantially identical in circuit configuration to one of pull-up and pull-down circuits included in an output buffer, adjusting impedance of a second replica buffer with updating a second code, the second replica buffer being substantially identical in circuit configuration to the other of the pull-up and pull-down circuits included in the output buffer, controlling a first latch circuit to hold the first code when the impedance of the first replica buffer reaches a first level, and controlling a second latch circuit to hold the second code when the impedance of the second replica buffer reaches a second level.
摘要翻译：一种方法包括发出校准命令并响应于校准命令执行校准操作。校准操作包括通过更新第一代码来调整第一副本缓冲器的阻抗，第一复制缓冲器在电路配置中基本上与包括在输出缓冲器中的上拉和下拉电路中的一个相同，调整第二代阻抗具有更新第二代码的副本缓冲器，所述第二复制缓冲器在电路配置中与包括在所述输出缓冲器中的所述上拉和下拉电路中的另一个基本相同，当所述阻抗的第一复制缓冲器达到第一电平，并且当第二复制缓冲器的阻抗达到第二电平时，控制第二锁存电路以保持第二代码。

2. 发明申请

US20100312956A1 Load reduced memory module 审中-公开
标题翻译：减少内存模块
公开(公告)号：US20100312956A1
公开(公告)日：2010-12-09
申请号：US12801325
申请日：2010-06-03
申请人： Atsushi Hiraishi , Toshio Sugano , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa , Shunichi Saito
发明人： Atsushi Hiraishi , Toshio Sugano , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa , Shunichi Saito
IPC分类号： G06F12/00 , G06F3/00
CPC分类号： G11C5/04 , G11C7/1045 , G11C7/1057 , G11C7/1084 , H01L2224/48091 , H01L2224/48227 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片和安装在模块基板上的多个数据寄存器缓冲器。至少两个存储器芯片被分配给每个数据寄存器缓冲器。每个数据寄存器缓冲器包括通过第一数据线连接到数据连接器的M个输入/输出端子（M是等于或大于1的正整数）和N个输入/输出端子（N是正整数等于大于2M），其经由第二和第三数据线连接到对应的存储器芯片，使得第二和第三数据线的数量是第一数据线的数量的N / M倍。根据本发明，由于第二和第三数据线的负载容量减少了很多，所以可以实现相当高的数据传输速率。

3. 发明申请

US20100097096A1 Calibration circuit, semiconductor device including the same, and data processing system 有权
标题翻译：校准电路，包括相同的半导体器件和数据处理系统
公开(公告)号：US20100097096A1
公开(公告)日：2010-04-22
申请号：US12654253
申请日：2009-12-15
申请人： Fumiyuki Osanai , Hiroki Fujisawa
发明人： Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： A semiconductor device adjusting an impedance level of an output buffer, includes a replica buffer circuit including a circuit configuration substantially identical to the output buffer, a counter circuit changing an impedance code to vary an impedance level of the replica buffer, a latch circuit temporarily holding the impedance code in response to a control signal, and an end-determining circuit producing the control signal in response to a lapse of a predetermined period from issuance of a calibration command, irrespective of a fact that the replica buffer has not yet reached a desirable impedance level.
摘要翻译：调整输出缓冲器的阻抗水平的半导体器件包括复制缓冲电路，其包括与输出缓冲器基本相同的电路配置，计数器电路改变阻抗代码以改变副本缓冲器的阻抗电平;锁存电路暂时保持响应于控制信号的阻抗代码，以及响应于从校准命令的发布而经过预定时间段而产生控制信号的终止确定电路，而不管复制缓冲器尚未达到期望的事实阻抗水平。

4. 发明申请

US20110248742A1 Calibration circuit, semiconductor device including the same, and data processing system 有权
标题翻译：校准电路，包括相同的半导体器件和数据处理系统
公开(公告)号：US20110248742A1
公开(公告)日：2011-10-13
申请号：US13067644
申请日：2011-06-16
申请人： Fumiyuki Osanai , Hiroki Fujisawa
发明人： Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： A method includes issuing a calibration command and performing a calibration operation in response to the calibration command. The calibration operation includes adjusting an impedance of a first replica buffer with updating a first code, the first replica buffer being substantially identical in circuit configuration to one of pull-up and pull-down circuits included in an output buffer, adjusting impedance of a second replica buffer with updating a second code, the second replica buffer being substantially identical in circuit configuration to the other of the pull-up and pull-down circuits included in the output buffer, controlling a first latch circuit to hold the first code when the impedance of the first replica buffer reaches a first level, and controlling a second latch circuit to hold the second code when the impedance of the second replica buffer reaches a second level.
摘要翻译：一种方法包括发出校准命令并响应于校准命令执行校准操作。校准操作包括通过更新第一代码来调整第一副本缓冲器的阻抗，第一复制缓冲器在电路配置中基本上与包括在输出缓冲器中的上拉和下拉电路中的一个相同，调整第二代阻抗具有更新第二代码的副本缓冲器，所述第二复制缓冲器在电路配置中与包括在所述输出缓冲器中的所述上拉和下拉电路中的另一个基本相同，当所述阻抗的第一复制缓冲器达到第一电平，并且当第二复制缓冲器的阻抗达到第二电平时，控制第二锁存电路以保持第二代码。

5. 发明申请

US20100309706A1 Load reduced memory module and memory system including the same 有权
标题翻译：负载减少的内存模块和包含相同的内存系统
公开(公告)号：US20100309706A1
公开(公告)日：2010-12-09
申请号：US12801326
申请日：2010-06-03
申请人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
发明人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
IPC分类号： G11C5/02 , G11C7/00
CPC分类号： G11C7/00 , G11C5/02 , G11C5/04 , G11C5/063 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/109 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片，多个数据寄存器缓冲器以及安装在模块PCB上的命令/地址/控制寄存器缓冲器。数据寄存器缓冲器与存储器芯片执行数据传输。命令/地址/控制寄存器缓冲器执行命令/地址/控制信号的缓冲并产生控制信号。缓冲的命令/地址/控制信号被提供给存储器芯片，并且控制信号被提供给数据寄存器缓冲器。根据本发明，由于数据寄存器缓冲器和存储器芯片之间的线路长度被缩短，可以实现相当高的数据传输速率。

6. 发明申请

US20090009213A1 Calibration circuit, semiconductor device including the same, and data processing system 有权
标题翻译：校准电路，包括相同的半导体器件和数据处理系统
公开(公告)号：US20090009213A1
公开(公告)日：2009-01-08
申请号：US12213962
申请日：2008-06-26
申请人： Fumiyuki Osanai , Hiroki Fujisawa
发明人： Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： A calibration circuit includes: replica buffers; an up-down counter that changes impedance codes of the replica buffers; latch circuits each holding the impedance codes; an end-determining circuit that activates the latch circuits in response to a completion of impedance adjustments of the replica buffers; and a 32 tCK cycle counter that forcibly activates the latch circuits in response to a lapse of a predetermined period since issuance of the calibration command. Thereby, even when the adjustment is not completed during one calibration period, a subsequent calibration operation can be executed from a previous point.
摘要翻译：校准电路包括：副本缓冲器; 一个改变复制缓冲器阻抗代码的升降计数器; 每个保持阻抗代码的锁存电路; 终端确定电路，响应于所述副本缓冲器的阻抗调整的完成来激活所述锁存电路; 以及32个tCK循环计数器，其响应于自发出校准命令而经过预定时间段而强制地启动锁存电路。因此，即使在一个校准周期期间调整未完成，也可以从先前的点执行随后的校准操作。

7. 发明授权

US07994812B2 Calibration circuit, semiconductor device including the same, and data processing system 有权
标题翻译：校准电路，包括相同的半导体器件和数据处理系统
公开(公告)号：US07994812B2
公开(公告)日：2011-08-09
申请号：US12654253
申请日：2009-12-15
申请人： Fumiyuki Osanai , Hiroki Fujisawa
发明人： Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H03K17/16
CPC分类号： H03K19/0005
摘要： A semiconductor device adjusting an impedance level of an output buffer, includes a replica buffer circuit including a circuit configuration substantially identical to the output buffer, a counter circuit changing an impedance code to vary an impedance level of the replica buffer, a latch circuit temporarily holding the impedance code in response to a control signal, and an end-determining circuit producing the control signal in response to a lapse of a predetermined period from issuance of a calibration command, irrespective of a fact that the replica buffer has not yet reached a desirable impedance level.
摘要翻译：调整输出缓冲器的阻抗水平的半导体器件包括复制缓冲电路，其包括与输出缓冲器基本相同的电路配置，计数器电路改变阻抗代码以改变副本缓冲器的阻抗电平;锁存电路暂时保持响应于控制信号的阻抗代码，以及响应于从校准命令的发布而经过预定时间段而产生控制信号的终止确定电路，而不管复制缓冲器尚未达到期望的事实阻抗水平。

8. 发明授权

US07569428B2 Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same 有权
标题翻译：制造半导体器件的方法，半导体器件及包括该器件的器件
公开(公告)号：US07569428B2
公开(公告)日：2009-08-04
申请号：US11525952
申请日：2006-09-25
申请人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
发明人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H01L21/82 , H01L23/52
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.
摘要翻译：公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据预定的布局。多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。

9. 发明申请

US20070069362A1 Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same 有权
标题翻译：制造半导体器件的方法，半导体器件及包括该器件的器件
公开(公告)号：US20070069362A1
公开(公告)日：2007-03-29
申请号：US11525952
申请日：2006-09-25
申请人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
发明人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.
摘要翻译：公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据预定的布局。多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。

10. 发明授权

US08422263B2 Load reduced memory module and memory system including the same 有权
标题翻译：负载减少的内存模块和包含相同的内存系统
公开(公告)号：US08422263B2
公开(公告)日：2013-04-16
申请号：US12801326
申请日：2010-06-03
申请人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
发明人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
IPC分类号： G11C5/06
CPC分类号： G11C7/00 , G11C5/02 , G11C5/04 , G11C5/063 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/109 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片，多个数据寄存器缓冲器以及安装在模块PCB上的命令/地址/控制寄存器缓冲器。数据寄存器缓冲器与存储器芯片执行数据传输。命令/地址/控制寄存器缓冲器执行命令/地址/控制信号的缓冲并产生控制信号。缓冲的命令/地址/控制信号被提供给存储器芯片，并且控制信号被提供给数据寄存器缓冲器。根据本发明，由于数据寄存器缓冲器和存储器芯片之间的线路长度被缩短，可以实现相当高的数据传输速率。

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