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1. 发明专利

JP2010098594A Demodulation circuit and method 审中-公开
标题翻译：解调电路和方法
公开(公告)号：JP2010098594A
公开(公告)日：2010-04-30
申请号：JP2008268806
申请日：2008-10-17
申请人： Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社
发明人： YOSHIDA MASAHIRO
IPC分类号： H04J11/00 , H03M13/01 , H04L1/00
摘要： PROBLEM TO BE SOLVED: To accomplish an OFDMA demodulation circuit which reduces circuit scale and power consumption.
SOLUTION: The present invention relates to a demodulation circuit wherein a plurality of burst regions are defined inside a frame defined by a symbol direction and a sub carrier direction, comprising: a symbol memory 31 for storing reception data obtained by demodulating a reception signal in the unit of a symbol; a transmission line estimation and compensation circuit 26 for performing transmission line estimation and compensation processing of the reception data stored in the symbol memory in the unit of a symbol; a buffer 32 for storing and outputting outputs of the transmission line estimation and compensation circuit in the unit of a block in error correction processing; and an error correction circuit 27 for performing error correction processing in the unit of a block on the transmission line estimation and compensation processed reception data output from the buffer.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：实现减少电路规模和功耗的OFDMA解调电路。解决方案：本发明涉及一种解调电路，其中在由符号方向和子载波方向定义的帧内部定义多个突发区域，包括：符号存储器31，用于存储通过解调接收获得的接收数据以符号为单位的信号; 用于以符号为单位对存储在符号存储器中的接收数据进行传输线估计和补偿处理的传输线路估计和补偿电路26; 缓冲器32，用于以误差校正处理为单位存储和输出传输线路估计和补偿电路的输出; 以及误差校正电路27，用于以传输线路估计的块为单位进行纠错处理，并从缓冲器输出补偿处理的接收数据。版权所有（C）2010，JPO＆INPIT

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