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1. 发明专利

JP2010010370A Semiconductor device and portable electronic device 有权
标题翻译：半导体器件和便携式电子器件
公开(公告)号：JP2010010370A
公开(公告)日：2010-01-14
申请号：JP2008167619
申请日：2008-06-26
申请人： Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社
发明人： OKAWA SHIGEMI
IPC分类号： H01L27/146 , H04N5/335 , H04N5/369 , H04N5/374
CPC分类号： H01L27/14603 , H01L27/14621 , H01L27/14641 , H04N5/3696 , H04N5/37457 , H04N9/045
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which includes a solid-state image pickup device with a plurality of pixel units arranged thereon, each of which has photoelectric conversion elements and a detection circuit for detecting a signal charge converted by the photoelectric conversion elements and which can easily enlarge the detection circuit formation area within the pixel unit. SOLUTION: The semiconductor device has two or more pixel units arranged in the shape of a matrix, each of which includes first to third photoelectric conversion elements for converting incident light into a signal charge, the light being received from the first to third colors, and a detection circuit which detects the signal charge converted by each of the first to third photoelectric conversion elements, and is used commonly by the photoelectric conversion elements, wherein a row of the first photoelectric conversion element and the detection circuit and that of the second and third photoelectric conversion elements are arranged adjacent to each other, or a column of the first photoelectric conversion element and the detection circuit and that of the second and third photoelectric conversion elements are arranged adjacent to each other. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其包括其上布置有多个像素单元的固态图像拾取器件，每个具有光电转换元件和检测电路，用于检测由光电转换元件，并且可以容易地扩大像素单元内的检测电路形成区域。解决方案：半导体器件具有排列成矩阵形状的两个或更多个像素单元，每个像素单元包括用于将入射光转换成信号电荷的第一至第三光电转换元件，所述光从第一至第三以及检测电路，其检测由第一至第三光电转换元件中的每一个转换的信号电荷，并且被光电转换元件共同使用，其中第一光电转换元件和检测电路的行以及第二和第三光电转换元件彼此相邻布置，或者第一光电转换元件和检测电路的列以及第二和第三光电转换元件的列彼此相邻布置。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2010056578A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010056578A
公开(公告)日：2010-03-11
申请号：JP2009277893
申请日：2009-12-07
申请人： Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社
发明人： IKEMASU SHINICHIRO , OKAWA SHIGEMI
IPC分类号： H01L21/8242 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To facilitate planarization by stabilizing a capacity of a DRAM and reducing the difference in height between a memory cell part and a peripheral circuit part. SOLUTION: A first contact plug is buried in a first insulating film on a memory cell transistor, and second and third insulating films different in etching characteristics are formed, and a contact window piercing the second and third insulating layers is formed, and a cylinder type storage electrode is formed, and the third insulating film is removed with the second insulating film as an etching stopper, and a capacitor insulating film and a conductive film are formed and are patterned to form a counter electrode, and the second insulating film also is removed in accordance with the counter electrode to form a memory cell, and a conductive film and an insulating film are formed on the first insulating film in a peripheral edge area, and a second contact plug is buried in them. An end part of the second insulating film is not brought into contact with the second contact plug. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了通过稳定DRAM的容量并减小存储单元部分和外围电路部分之间的高度差来促进平坦化。解决方案：第一接触插塞埋在存储单元晶体管的第一绝缘膜中，形成不同蚀刻特性的第二和第三绝缘膜，形成穿透第二绝缘层和第三绝缘层的接触窗口，形成圆柱型存储电极，用第二绝缘膜作为蚀刻停止层去除第三绝缘膜，形成电容器绝缘膜和导电膜，并形成对电极，第二绝缘膜还根据对电极去除以形成存储单元，并且在周边区域中的第一绝缘膜上形成导电膜和绝缘膜，并且在其中埋入第二接触插塞。第二绝缘膜的端部不与第二接触插塞接触。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2010050474A Semiconductor device, and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010050474A
公开(公告)日：2010-03-04
申请号：JP2009241474
申请日：2009-10-20
申请人： Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社
发明人： IKEMASU SHINICHIRO , OKAWA SHIGEMI
IPC分类号： H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device such as a DRAM wherein a contact window is formed in a conductive layer different in height from a substrate. SOLUTION: First conductive patterns 19, 20, a first insulation film 26, a second insulation film 30 having a different etching characteristic, a third insulation film 52, a storage electrode 39, a capacitor insulation film, a counter electrode 40 and a fourth insulation film 41 having a different etching characteristics, are formed on a semiconductor substrate 16; a mask having a first opening above the first conductive patterns 19, 20 and a second opening above the counter electrode 40 is formed; the fourth insulation film 41 and the second insulation film 30 below the first opening are etched by using the first insulation film 26 as a stopper; the fourth insulation film 41 and the counter electrode 40 below the second opening are etched by using the third insulation film 52 as a stopper; the first insulation film 26 below the first opening is etched to form a first contact hole 44; the third insulation film 52 below the second opening is etched by using the second insulation film 30 as a stopper to form a second contact hole 42; and a conductive material is embedded. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种诸如DRAM的半导体器件，其中接触窗形成在与衬底高度不同的导电层中。解决方案：第一导电图案19,20，第一绝缘膜26，具有不同蚀刻特性的第二绝缘膜30，第三绝缘膜52，存储电极39，电容器绝缘膜，对电极40和在半导体衬底16上形成具有不同蚀刻特性的第四绝缘膜41; 形成具有在第一导电图案19,20上方的第一开口和在对电极40上方的第二开口的掩模; 通过使用第一绝缘膜26作为止动件来蚀刻第一开口下方的第四绝缘膜41和第二绝缘膜30; 通过使用第三绝缘膜52作为止动件来蚀刻在第二开口下方的第四绝缘膜41和对电极40; 在第一开口下方的第一绝缘膜26被蚀刻以形成第一接触孔44; 通过使用第二绝缘膜30作为止动件来蚀刻第二开口下方的第三绝缘膜52，以形成第二接触孔42; 并且嵌入导电材料。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2009147174A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2009147174A
公开(公告)日：2009-07-02
申请号：JP2007323921
申请日：2007-12-14
申请人： Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社
发明人： OKAWA SHIGEMI
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L23/5286 , G11C11/412 , H01L27/11 , H01L27/1104 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To considerably increase the capacity of a storage node and sufficiently meet the demand for further miniaturization without an increase in the number of manufacturing processes and in the manufacturing cost with an extremely simple configuration.
SOLUTION: Conductive layers CL1, CL2 are arranged on the upper layer part of each of storage nodes SN1, SN2 so as to be electrically connected with the storage nodes SN1, SN2 of each of inverters IV1, IV2. On the upper layer part and its neighboring layer part, a V
DD layer and a V
SS layer are arranged, and a parasitic capacitance is produced by capacitive coupling between the conductive layers CL1, CL2 and the V
DD layer, between the conductive layers CL1, CL2 and the V
SS layer, and between the conductive layers CL1, CL2. Due to this configuration, the capacity of the storage nodes SN1, SN2 is increased as a result.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了显着增加存储节点的容量并充分满足进一步小型化的需求，而不增加制造过程的数量和以非常简单的配置的制造成本。解决方案：导电层CL1，CL2布置在每个存储节点SN1，SN2的上层部分上，以与每个逆变器IV1，IV2的存储节点SN1，SN2电连接。在上层部分及其相邻层部分上布置有V SB SB 层和V SS 层，并且通过导电层之间的电容耦合产生寄生电容 CL1，CL2和V DD 层之间，导电层CL1，CL2和V SS 层之间以及导电层CL1，CL2之间。由于这种配置，结果，存储节点SN1，SN2的容量增加。版权所有（C）2009，JPO＆INPIT

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