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1. 发明申请

US20110210343A1 SEMICONDUCTOR WAFER 审中-公开
公开(公告)号：US20110210343A1
公开(公告)日：2011-09-01
申请号：US12859825
申请日：2010-08-20
申请人： Fu-Bang CHEN , Kuo-Lung Fang , Kun-Fu Huang , Te-Chung Wang
发明人： Fu-Bang CHEN , Kuo-Lung Fang , Kun-Fu Huang , Te-Chung Wang
IPC分类号： H01L33/00 , H01L23/00
CPC分类号： H01L33/12 , H01L33/007 , H01L33/20
摘要： A semiconductor wafer includes a substrate, a first separating structure and a semiconductor stacked layer structure. The substrate has a first surface. The first separating structure is formed on the first surface to divide the first surface into a plurality of independent regions. The minimum area of each of the regions is more than or equal to one square inch. The semiconductor stacked layer structure is disposed on the first surface and the first separating structure. The semiconductor wafer can prevent bowing of the semiconductor wafer during an epitaxial growth process so as to enhance quality of the semiconductor wafer.
摘要翻译：半导体晶片包括基板，第一分离结构和半导体叠层结构。衬底具有第一表面。第一分离结构形成在第一表面上以将第一表面分成多个独立区域。每个区域的最小面积大于或等于1平方英寸。半导体堆叠层结构设置在第一表面和第一分离结构上。半导体晶片可以在外延生长工艺期间防止半导体晶片弯曲，从而提高半导体晶片的质量。

2. 发明授权

US08253160B2 Light-emitting diode chip structure and fabrication method thereof 有权
标题翻译：发光二极管芯片结构及其制造方法
公开(公告)号：US08253160B2
公开(公告)日：2012-08-28
申请号：US13050677
申请日：2011-03-17
申请人： Jun-Rong Chen , Chi-Wen Kuo , Kun-Fu Huang , Jui-Yi Chu , Kuo-Lung Fang
发明人： Jun-Rong Chen , Chi-Wen Kuo , Kun-Fu Huang , Jui-Yi Chu , Kuo-Lung Fang
IPC分类号： H01L33/20
CPC分类号： H01L33/20 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/02647 , H01L33/007 , H01L33/382 , H01L33/387
摘要： A light-emitting diode chip structure including a conductive substrate, a semiconductor stacking layer and a patterned seed crystal layer is provided. The conductive substrate has a surface. The surface has a first region and a second region alternately distributed over the surface. The semiconductor stacking layer is disposed on the conductive substrate, and the surface of the conductive substrate faces the semiconductor stacking layer. The patterned seed crystal layer is disposed on the first region of the surface of the conductive substrate and between the conductive substrate and the semiconductor stacking layer. The patterned seed crystal layer separates the semiconductor stacking layer from the first region. The semiconductor stacking layer covers the patterned seed crystal layer and the second region, and is electrically connected to the conductive substrate through the second region. A fabrication method of the light-emitting diode chip structure is also provided.
摘要翻译：提供了包括导电基板，半导体堆叠层和图案化晶种层的发光二极管芯片结构。导电基板具有表面。表面具有交替地分布在表面上的第一区域和第二区域。半导体层叠层设置在导电性基板上，导电性基板的表面面向半导体层叠层。图案化晶种层设置在导电基板的表面的第一区域上，并且在导电基板和半导体堆叠层之间。图案化晶种层将半导体层叠层与第一区域分开。半导体堆叠层覆盖图案化晶种层和第二区域，并且通过第二区域电连接到导电基板。还提供了发光二极管芯片结构的制造方法。

3. 发明申请

US20120168712A1 HIGH BRIGHT LIGHT EMITTING DIODE 审中-公开
标题翻译：高亮度发光二极管
公开(公告)号：US20120168712A1
公开(公告)日：2012-07-05
申请号：US13329704
申请日：2011-12-19
申请人： Kuo-Lung Fang , Kun-Fu Huang , Chun-Jong Chang , Chi-Wen Kuo , Jun-Rong Chen , Chih-wei Chao
发明人： Kuo-Lung Fang , Kun-Fu Huang , Chun-Jong Chang , Chi-Wen Kuo , Jun-Rong Chen , Chih-wei Chao
IPC分类号： H01L33/04 , H01L33/60
CPC分类号： H01L33/382 , H01L33/46
摘要： A high bright LED comprises a substrate, a conductive layer, a first semiconductor layer, a luminous layer, a second semiconductor layer, a first electrode, a second electrode and an insulation structure. The conductive layer, the first semiconductor layer, the luminous layer and the second semiconductor layer are disposed upwards from an upper solder layer of the substrate in order. The first electrode is electrically connected to the conductive layer The second electrode penetrates through the conductive layer, the first semiconductor layer and the luminous layer to make the upper solder and the second semiconductor layer electrically connected. The insulation structure comprises at least two passivation layers peripherally wrapping the second electrode. The thicknesses of the at least two passivation layers are conformed to the distributed Bragg reflection technique to make the passivation layers jointly used as a reflector with high reflectance.
摘要翻译：高亮度LED包括基板，导电层，第一半导体层，发光层，第二半导体层，第一电极，第二电极和绝缘结构。导电层，第一半导体层，发光层和第二半导体层依次从衬底的上焊料层向上设置。第一电极电连接到导电层。第二电极穿过导电层，第一半导体层和发光层，以使上焊料和第二半导体层电连接。绝缘结构包括至少两个钝化层，其外围地缠绕第二电极。至少两个钝化层的厚度符合分布布拉格反射技术，以使钝化层联合用作具有高反射率的反射器。

4. 发明申请

US20100221494A1 METHOD FOR FORMING SEMICONDUCTOR LAYER 审中-公开
标题翻译：形成半导体层的方法
公开(公告)号：US20100221494A1
公开(公告)日：2010-09-02
申请号：US12465655
申请日：2009-05-14
申请人： Chang-Ming Lu , Chih-Wei Chao , Te-Chung Wang , Kuo-Lung Fang , Chun-Jong Chang
发明人： Chang-Ming Lu , Chih-Wei Chao , Te-Chung Wang , Kuo-Lung Fang , Chun-Jong Chang
IPC分类号： B32B3/00 , H01L21/20
CPC分类号： H01L21/02647 , C30B25/02 , C30B29/406 , H01L21/0237 , H01L21/02433 , H01L21/02639 , Y10T428/24479
摘要： A method for forming a semiconductor layer includes following steps. First, an epitaxial substrate having at least a first growth region and at least a second growth region is provided. An area ratio of C plane to R plane in the first growth region is greater than 52/48. An epitaxial process is then performed on the epitaxial substrate to form a semiconductor layer. During the epitaxial process, a semiconductor material is selectively grown on the first growth region, and then the semiconductor material is laterally overgrown on the second growth region and covers the same.
摘要翻译：形成半导体层的方法包括以下步骤。首先，提供具有至少第一生长区和至少第二生长区的外延衬底。第一生长区域中C面与R面的面积比大于52/48。然后在外延衬底上进行外延工艺以形成半导体层。在外延工艺期间，半导体材料选择性地生长在第一生长区域上，然后半导体材料在第二生长区域上横向长满而覆盖。

5. 发明授权

US09570653B2 Light-emitting semiconductor structure and method for fabricating light-emitting diode device 有权
标题翻译：发光半导体结构及其制造方法
公开(公告)号：US09570653B2
公开(公告)日：2017-02-14
申请号：US13590474
申请日：2012-08-21
申请人： Kuo-Lung Fang , Chi-Wen Kuo , Jun-Rong Chen , Chih-Hao Yang
发明人： Kuo-Lung Fang , Chi-Wen Kuo , Jun-Rong Chen , Chih-Hao Yang
IPC分类号： H01L33/20 , H01L33/50 , H01L33/06 , H01L33/00 , H01L33/08
CPC分类号： H01L33/20 , H01L33/0079 , H01L33/06 , H01L33/08 , H01L33/50 , H01L33/505
摘要： A method for fabricating a light-emitting device is provided. The method includes: providing a substrate; forming a sacrificial dielectric layer on the substrate, wherein the sacrificial dielectric layer is a structure containing voids; forming a buffer layer on the sacrificial dielectric layer; forming an epitaxial light-emitting structure on the buffer layer; forming a metal bonding layer on the epitaxial light-emitting structure; bonding the metal bonding layer to a thermally conductive substrate; and wet etching the sacrificial dielectric layer for to remove the substrate.
摘要翻译：提供一种制造发光器件的方法。该方法包括：提供衬底; 在所述衬底上形成牺牲电介质层，其中所述牺牲绝缘层是包含空隙的结构; 在所述牺牲介电层上形成缓冲层; 在缓冲层上形成外延发光结构; 在外延发光结构上形成金属结合层; 将金属粘结层粘合到导热基板上; 并湿蚀刻牺牲介电层以去除衬底。

6. 发明授权

US08431929B2 Semiconductor structures 有权
标题翻译：半导体结构
公开(公告)号：US08431929B2
公开(公告)日：2013-04-30
申请号：US12633975
申请日：2009-12-09
申请人： Kuo-Lung Fang , Chih-Chun Yang , Han-Tu Lin
发明人： Kuo-Lung Fang , Chih-Chun Yang , Han-Tu Lin
IPC分类号： H01L29/40 , H01L31/036 , H01L31/062 , H01L27/01 , H01L27/12
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/124
摘要： A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate disposed thereon, an insulation layer disposed on the substrate and overlying the gate, a patterned semiconductor layer disposed on the insulation layer, a source and a drain disposed on the patterned semiconductor layer, a protective layer overlying the insulation layer, the source and the boundary of the drain to expose a portion of the drain, and a pixel electrode disposed on the substrate, overlying the protective layer overlying the boundary of the drain, electrically connected to the exposed drain.
摘要翻译：提供半导体结构。半导体结构包括衬底，设置在其上的栅极，设置在衬底上并覆盖栅极的绝缘层，设置在绝缘层上的图案化半导体层，设置在图案化半导体层上的源极和漏极，保护层覆盖所述绝缘层，所述漏极的源极和边界以暴露所述漏极的一部分，以及设置在所述衬底上的像素电极，覆盖所述保护层，所述保护层覆盖所述漏极的边界，电连接到所述暴露的漏极。

7. 发明授权

US08349631B2 Method for fabricating thin film transistor array substrate 有权
标题翻译：薄膜晶体管阵列基板的制造方法
公开(公告)号：US08349631B2
公开(公告)日：2013-01-08
申请号：US13225568
申请日：2011-09-06
申请人： Shine-Kai Tseng , Han-Tu Lin , Shiun-Chang Jan , Kuo-Lung Fang
发明人： Shine-Kai Tseng , Han-Tu Lin , Shiun-Chang Jan , Kuo-Lung Fang
IPC分类号： H01L21/338 , H01L31/112
CPC分类号： H01L27/1248 , H01L27/1288
摘要： A method for fabricating a TFT array substrate includes following steps. A gate pattern and a first pad pattern are formed on a substrate. A gate insulation layer and a semiconductor layer covering the two patterns are sequentially formed. A patterned photoresist layer having different resist blocks is formed, and patterns and thicknesses of the resist blocks in different regions are adjusted. The semiconductor layer and the gate insulation layer above the first pad pattern are removed through performing an etching process and reducing a thickness of the patterned photoresist layer. After removing the patterned photoresist layer, a source pattern, a drain pattern, and a second pad pattern electrically connected to the first pad pattern are formed. A patterned passivation layer is formed on the gate insulation layer and has a second opening exposing the source pattern or the drain pattern and a third opening exposing the second pad pattern.
摘要翻译：制造TFT阵列基板的方法包括以下步骤。在基板上形成栅极图案和第一焊盘图案。依次形成覆盖这两个图案的栅绝缘层和半导体层。形成具有不同抗蚀剂块的图案化光致抗蚀剂层，并且调整不同区域中的抗蚀剂块的图案和厚度。通过执行蚀刻工艺并减小图案化光致抗蚀剂层的厚度来去除第一焊盘图案上方的半导体层和栅极绝缘层。在去除图案化的光致抗蚀剂层之后，形成电连接到第一焊盘图案的源图案，漏极图案和第二焊盘图案。图案化的钝化层形成在栅极绝缘层上，并且具有暴露源图案或漏极图案的第二开口和暴露第二焊盘图案的第三开口。

8. 发明申请

US20110318855A1 METHOD FOR FABRICATING LIGHT EMITTING DIODE CHIP 有权
标题翻译：用于制造发光二极管芯片的方法
公开(公告)号：US20110318855A1
公开(公告)日：2011-12-29
申请号：US13220693
申请日：2011-08-30
申请人： Kuo-Lung Fang , Chien-Sen Weng , Chih-Wei Chao
发明人： Kuo-Lung Fang , Chien-Sen Weng , Chih-Wei Chao
IPC分类号： H01L33/44
CPC分类号： H01L33/387 , H01L33/382 , H01L33/44
摘要： A method for fabricating a light emitting diode chip is provided. Firstly, a semiconductor device layer is formed on a substrate. Afterwards, a current spreading layer is formed on a portion of the semiconductor device layer. Then, a current blocking layer and a passivation layer are formed on a portion of the semiconductor device layer not covered by the current spreading layer. Finally, a first electrode is formed on the current blocking layer and the current spreading layer. Moreover, a second electrode is formed on the semiconductor device layer.
摘要翻译：提供一种制造发光二极管芯片的方法。首先，在基板上形成半导体器件层。之后，在半导体器件层的一部分上形成电流扩散层。然后，在未被电流扩展层覆盖的半导体器件层的一部分上形成电流阻挡层和钝化层。最后，在电流阻挡层和电流扩展层上形成第一电极。此外，在半导体器件层上形成第二电极。

9. 发明申请

US20110165705A1 Method for Fabricating LED Chip Comprising Reduced Mask Count and Lift-Off Processing 有权
标题翻译：制造LED芯片的方法包括减少掩模计数和剥离处理
公开(公告)号：US20110165705A1
公开(公告)日：2011-07-07
申请号：US13046606
申请日：2011-03-11
申请人： Kuo-Lung Fang , Chien-Sen Weng , Chih-Wei Chao
发明人： Kuo-Lung Fang , Chien-Sen Weng , Chih-Wei Chao
IPC分类号： H01L33/36
CPC分类号： H01L33/44 , H01L33/387 , Y10S438/951
摘要： A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.
摘要翻译：提供一种制造发光二极管芯片的方法。在该方法中，应用半色调掩模处理，灰度色调处理或多色调掩模处理，并与剥离处理相结合，以进一步减少发光二极管芯片的处理步骤。在本发明中，一些部件也可以通过相同的工艺同时形成，以减少发光二极管芯片的工艺步骤。因此，本发明中提供的发光二极管的制造方法降低了用于制造发光二极管的成本和时间。

10. 发明申请

US20110159614A1 Method for Fabricating LED Chip Comprising Reduced Mask Count and Lift-Off Processing 有权
公开(公告)号：US20110159614A1
公开(公告)日：2011-06-30
申请号：US13046632
申请日：2011-03-11
申请人： Kuo-Lung Fang , Chien-Sen Weng , Chih-Wei Chao
发明人： Kuo-Lung Fang , Chien-Sen Weng , Chih-Wei Chao
IPC分类号： H01L33/48
CPC分类号： H01L33/44 , H01L33/387 , Y10S438/951
摘要： A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

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