专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2013150316A Pipeline analog to digital converter with reduced power consumption 有权
标题翻译：管道模拟到数字转换器与降低功耗
公开(公告)号：JP2013150316A
公开(公告)日：2013-08-01
申请号：JP2012277272
申请日：2012-12-19
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： DOUGLAS A GARRITY
IPC分类号： H03M1/44 , H03M1/12
CPC分类号： H03M1/1215 , H03M1/1245
摘要： PROBLEM TO BE SOLVED: To provide a pipeline analog to digital (A/D) converter which has both advantages of a high input sample rate and low power consumption by allowing all pipeline stages, excepting for a first pipeline stage, to operate in a frequency that is a certain fraction of an input sample rate.SOLUTION: A first stage 110 has an internal operation frequency that is a sample rate for all A/D converters and samples an input signal on the same clock edge in each sample. A subsequent pipeline stage 120 includes a parallel input sampling circuit which samples a provided input signal at a reduced rate. The input sampling circuit operates in a reduced frequency, thereby reducing power consumed by these stages. The input signal is sampled on the same clock edge for each sample, thereby solving the problem of frequency response image generated relating to an A/D converter architecture sampling an input signal on two or more clock edges.
摘要翻译：要解决的问题：提供一种流水线模数（A / D）转换器，其具有高输入采样率和低功耗的优点，允许除第一流水线级之外的所有流水线级以频率工作这是输入采样率的一定分数。解决方案：第一级110具有作为所有A / D转换器的采样率的内部操作频率，并对每个采样中的相同时钟沿上的输入信号采样。随后的流水线级120包括以降低的速率对所提供的输入信号进行采样的并行输入采样电路。输入采样电路以降低的频率工作，从而降低这些级的功耗。对于每个采样，输入信号在相同的时钟沿进行采样，从而解决与在两个或更多个时钟边沿上对输入信号进行采样的A / D转换器架构产生的频率响应图像的问题。

2. 发明专利

JP2014138425A Digital to analog converter with current steering source for reduced glitch energy error 有权
标题翻译：数字转换器具有电流转向源，用于降低玻璃能量误差
公开(公告)号：JP2014138425A
公开(公告)日：2014-07-28
申请号：JP2014005145
申请日：2014-01-15
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： MOHAMMAD NIZAM U KABIR , BRANDT BRASWELL , DOUGLAS A GARRITY
IPC分类号： H03M1/74 , H03M1/08
CPC分类号： H03M1/661 , H03M1/0863 , H03M1/68 , H03M1/742
摘要： PROBLEM TO BE SOLVED: To provide a system and method for reducing glitch energy error and achieving accurate step when changing from one digital value to another.SOLUTION: A current steering source for a digital to analog converter (DAC) uses a replica biasing and a master amplifier buffer to enable the use of different threshold devices to achieve very fast signal response and to reduce rising and falling edge mismatch.
摘要翻译：要解决的问题：提供一种用于减少毛刺能量误差并在从一个数字值变为另一个数字值时实现精确步骤的系统和方法。解决方案：数模转换器（DAC）的电流转向源使用复制偏置和主放大器缓冲器使得能够使用不同的阈值器件来实现非常快的信号响应并减少上升沿和下降沿的不匹配。

3. 发明专利

JP2013246166A Vehicle-borne radar systems with continuous-time, sigma delta analog-to-digital converters, and methods of their operation 审中-公开
标题翻译：具有连续时间的车载雷达雷达系统，SIGMA DELTA模拟数字转换器及其操作方法
公开(公告)号：JP2013246166A
公开(公告)日：2013-12-09
申请号：JP2013103808
申请日：2013-05-16
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： BRANDT BRASWELL , DOUGLAS A GARRITY , MOHAMMAD NIZAM U KABIR
IPC分类号： G01S13/93 , B60R21/00 , G01S13/34 , G08G1/16
CPC分类号： G01S13/34 , G01S7/352 , G01S13/931 , G01S2013/9314 , G01S2013/9321 , G01S2013/9325 , G01S2013/9332 , G01S2013/9342 , G01S2013/9346 , G01S2013/9375 , G01S2013/9378 , G01S2013/9385 , H03M3/424 , H03M3/448 , H03M3/452 , H03M3/454
摘要： PROBLEM TO BE SOLVED: To provide vehicle-borne radar systems, and methods of their operation.SOLUTION: The vehicle-borne radar system includes a transmit path and a first receive path. The transmit path is capable of producing a signal for transmission over an air interface (e.g., a frequency modulated continuous wave (FMCW) signal). The receive path includes a continuous-time (CT) sigma delta analog-to-digital converter (ADC), and the receive path is capable of receiving a reflected version of the signal from the air interface, and converting the reflected version along the receive path into a sequence of digital samples using the CT sigma delta ADC. In an embodiment, the transmit path and the receive path are integrated onto a single integrated circuit.
摘要翻译：要解决的问题：提供车载雷达系统及其运行方法。解决方案：车载雷达系统包括发射路径和第一接收路径。发射路径能够产生用于通过空中接口传输的信号（例如，调频连续波（FMCW）信号）。接收路径包括连续时间（CT）Σ-Δ模数转换器（ADC），并且接收路径能够从空中接口接收信号的反射版本，并沿接收器转换反射版本使用CT西格玛Delta ADC的数字采样序列。在一个实施例中，发射路径和接收路径被集成到单个集成电路上。

4. 发明专利

JP2013229868A Sample and hold circuit 有权
标题翻译：示例和保持电路
公开(公告)号：JP2013229868A
公开(公告)日：2013-11-07
申请号：JP2013074320
申请日：2013-03-29
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： MOHAMMAD NIZAM U KABIR , DOUGLAS A GARRITY , RAKESH SHIWALE
IPC分类号： H03K17/00 , H03K17/687 , H03M1/12
CPC分类号： G11C27/02 , G11C27/024 , G11C27/026
摘要： PROBLEM TO BE SOLVED: To provide a sample and hold circuit.SOLUTION: The circuit comprises: a plurality of switches; a first capacitor; an operational amplifier having a first input selectively coupled to the first capacitor and an output; and a second capacitor and a third capacitor both selectively coupled to the first capacitor and both selectively coupled between the first input of the operational amplifier and the output of the operational amplifier. The plurality of switches are configured to receive a plurality of control signals. Thereby, the first capacitor is configured to sample an input signal in a sample phase and to transfer a charge to one of the second capacitor and the third capacitor in a hold phase; and the second capacitor and the third capacitor are configured to alternate holding the transferred charge and resetting in any back-to-back hold phases.
摘要翻译：要解决的问题：提供采样和保持电路。解决方案：电路包括：多个开关; 第一电容器; 具有选择性地耦合到所述第一电容器的第一输入和输出的运算放大器; 以及第二电容器和第三电容器，其选择性地耦合到所述第一电容器并且都选择性地耦合在所述运算放大器的第一输入端和所述运算放大器的输出端之间。多个开关被配置为接收多个控制信号。因此，第一电容器被配置为在采样相位中对输入信号进行采样，并在保持阶段将电荷传送到第二电容器和第三电容器之一; 并且第二电容器和第三电容器被配置为交替地保持传送的电荷并且在任何背对背保持阶段中复位。

5. 发明专利

JP2013198151A Sample hold circuit and differential sample hold circuit 有权
标题翻译：样品保持电路和差示样品保持电路
公开(公告)号：JP2013198151A
公开(公告)日：2013-09-30
申请号：JP2013034809
申请日：2013-02-25
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： DOUGLAS A GARRITY , AHMAD H ATRISS
IPC分类号： H03M1/12 , G11C27/02 , H03K17/687
CPC分类号： G11C27/026
摘要： PROBLEM TO BE SOLVED: To provide a sample hold circuit which does not have a reset period.SOLUTION: The sample hold circuit is provided. The circuit includes a first switch configured so as to receive an input, a second switch connected to a second end part of the first switch, a first capacitor connected to the second end part of the first switch, a third switch connected to a second end part of the first capacitor, a fourth switch connected between the second end part and the ground, an operational amplifier having a first input connected to a second end part of the third switch, a second input connected to the ground and an output connected to a second end part of the second switch, a fifth switch connected to the second end part of the third switch, a second capacitor connected between the output of the operational amplifier and a second end part of the fifth switch, and a sixth switch connected between a second end part of the second capacitor and the ground.
摘要翻译：要解决的问题：提供不具有复位周期的采样保持电路。解决方案：提供采样保持电路。该电路包括被配置为接收输入的第一开关，连接到第一开关的第二端部的第二开关，连接到第一开关的第二端部的第一电容器，连接到第二端部的第三开关第一电容器的一部分，连接在第二端部和地之间的第四开关，具有连接到第三开关的第二端部的第一输入端的运算放大器，连接到地的第二输入端和连接到地第二开关的第二端部，连接到第三开关的第二端部的第五开关，连接在运算放大器的输出端和第五开关的第二端部之间的第二电容器，以及连接在第三开关第二电容器和地的第二端部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式