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1. 发明申请

US20110115019A1 CMOS COMPATIBLE LOW GATE CHARGE LATERAL MOSFET 审中-公开
标题翻译： CMOS兼容低栅极充电侧向MOSFET
公开(公告)号：US20110115019A1
公开(公告)日：2011-05-19
申请号：US12618546
申请日：2009-11-13
申请人： Frederick Perry Giles , Joel M. McGregor , Stephen McCormack
发明人： Frederick Perry Giles , Joel M. McGregor , Stephen McCormack
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0878 , H01L29/1083 , H01L29/42368 , H01L29/7816 , H01L29/7831
摘要： A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a switching gate positioned over a first portion of a channel region of the substrate, and a second portion forming a static gate formed over a second portion of the channel region and a transition region of the substrate. The static plate also extends over a drift region of the substrate, where the drift region is under a field oxide filled trench formed in the substrate. A switching voltage is applied to the switching gate and a constant voltage is applied to the static gate.
摘要翻译：分离栅功率晶体管包括横向配置的功率MOSFET，其包括掺杂硅衬底，形成在衬底的表面上的栅氧化层，以及形成在栅极氧化物层上的分裂多晶硅层。多晶硅层被切割成两个电隔离部分，第一部分形成位于衬底的沟道区域的第一部分上方的开关栅极，以及形成在沟道区域的第二部分上形成的静态栅极的第二部分，以及过渡区域。静态板还在衬底的漂移区域上延伸，其中漂移区域位于形成在衬底中的场氧化物填充沟槽之下。切换电压施加到开关栅极，并且恒定电压施加到静态栅极。

2. 发明授权

US07494876B1 Trench-gated MIS device having thick polysilicon insulation layer at trench bottom and method of fabricating the same 失效
标题翻译：在沟槽底部具有厚多晶硅绝缘层的沟槽门式MIS器件及其制造方法
公开(公告)号：US07494876B1
公开(公告)日：2009-02-24
申请号：US11112403
申请日：2005-04-21
申请人： Frederick Perry Giles , Kam Hong Lui
发明人： Frederick Perry Giles , Kam Hong Lui
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42368 , H01L29/66734
摘要： In a trench-gated MIS semiconductor device, a slug of undoped polysilicon is deposited at the bottom of the trench to protect the gate oxide in this area against the high electric fields that can occur in this area. The slug is formed over a thick oxide layer at the bottom of the trench. A process of fabricating the MOSFET includes the steps of growing a thick oxide layer on the sidewalls and bottom of the trench, depositing a polysilicon layer which remains undoped, etching the polysilicon layer to form the plug, etching the exposed portion of the thick oxide layer, growing a gate oxide layer and an oxide layer over the plug, and depositing and doping a polysilicon layer which serves as the gate electrode. In an alternative embodiment, the oxide layer overlying the plug is etched before the gate polysilicon is deposited such that the dopant introduced into the gate polysilicon migrates into the polysilicon plug. In this embodiment, the polysilicon plug is in electrical contact with the gate polysilicon layer and is separated from the drain by the thick oxide layer.
摘要翻译：在沟槽门控MIS半导体器件中，未掺杂的多晶硅块被沉积在沟槽的底部，以保护该区域中的栅极氧化物抵抗可能在该区域中发生的高电场。块状物形成在沟槽底部的厚氧化物层上。制造MOSFET的过程包括以下步骤：在沟槽的侧壁和底部生长厚的氧化物层，沉积保留未掺杂的多晶硅层，蚀刻多晶硅层以形成插塞，蚀刻厚氧化物层的暴露部分在插头上生长栅极氧化层和氧化物层，以及沉积和掺杂用作栅电极的多晶硅层。在替代实施例中，在栅极多晶硅被沉积之前蚀刻覆盖在插塞上的氧化物层，使得引入到栅极多晶硅中的掺杂剂迁移到多晶硅插塞中。在该实施例中，多晶硅插塞与栅极多晶硅层电接触并且通过厚氧化物层与漏极分离。

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