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1. 发明授权

US4823259A High speed buffer store arrangement for quick wide transfer of data 失效
标题翻译：高速缓冲存储布置，可快速传输数据
公开(公告)号：US4823259A
公开(公告)日：1989-04-18
申请号：US213506
申请日：1988-06-23
申请人： Frederick J. Aichelmann, Jr. , Rex H. Blumberg , David Meltzer , James H. Pomerene , Thomas R. Puzak , Rudolph N. Rechtschaffen , Frank J. Sparacio
发明人： Frederick J. Aichelmann, Jr. , Rex H. Blumberg , David Meltzer , James H. Pomerene , Thomas R. Puzak , Rudolph N. Rechtschaffen , Frank J. Sparacio
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0897
摘要： A high speed buffer store arrangement for use in a data processing system having multiple cache buffer storage units in a hierarchial arrangement permits fast transfer of wide data blocks. On each cache chip, input and output latches are integrated thus avoiding separate intermediate buffering. Input and output latches are interconnected by 64-byte wide data buses so that data blocks can be shifted rapidly from one cache hierarchy level to another and back. Chip-internal feedback connections from output to input latches allow data blocks to be selectively reentered into a cache after reading. An additional register array is provided so that data blocks can be furnished again after transfer from cache to main memory or CPU without accessing the respective cache. Wide data blocks can be transferred within one cycle, thus tying up caches much less in transfer operations, so that they have increased availability.
摘要翻译：用于具有分级布置的多个高速缓存存储单元的数据处理系统中的高速缓冲存储装置允许宽数据块的快速传送。在每个缓存芯片上，集成了输入和输出锁存器，从而避免了单独的中间缓冲。输入和输出锁存器通过64字节的宽数据总线互连，使得数据块可以从一个缓存层次级别快速移动到另一个高速缓存层级。从输出到输入锁存器的芯片内部反馈连接允许数据块在读取之后被选择性地重新进入高速缓存。提供了一个附加的寄存器阵列，使得在从高速缓存传送到主存储器或CPU之后再次可以提供数据块，而不访问相应的高速缓存。广泛的数据块可以在一个周期内传输，从而在传输操作中减少高速缓存，从而增加可用性。

2. 发明授权

US07885359B2 Sampling demodulator for amplitude shift keying (ASK) radio receiver 有权
标题翻译：用于幅移键控（ASK）无线电接收机的采样解调器
公开(公告)号：US07885359B2
公开(公告)日：2011-02-08
申请号：US11839347
申请日：2007-08-15
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03D1/24
CPC分类号： H04L27/06 , H04L7/0331 , H04L25/068
摘要： A method, algorithm, circuits, and/or systems for amplitude shift keying (ASK) modulation are disclosed. In one embodiment, a sampling demodulator includes a comparator configured to compare an ASK modulated input to a predetermined voltage level and provide a comparison result, a pulse stretcher with a sampler configured to sample the comparison result a plurality of times for each of a plurality of cycles of the ASK modulated input to generate a bit stream and digital logic configured to determine a value for each data bit in the ASK modulated input from the bit stream, and a digital filter configured to filter an output of the digital logic, thereby providing a demodulated signal.
摘要翻译：公开了一种用于幅移键控（ASK）调制的方法，算法，电路和/或系统。在一个实施例中，采样解调器包括比较器，其被配置为将ASK调制输入与预定电压电平进行比较并提供比较结果;脉冲展宽器，其具有被配置为针对多个 ASK调制输入的周期以产生比特流，以及数字逻辑，被配置为确定来自比特流的ASK调制输入中的每个数据比特的值，以及数字滤波器，其被配置为对数字逻辑的输出进行滤波，从而提供解调信号。

3. 发明申请

US20080267313A1 Dual Demodulation Mode AM Radio 失效
标题翻译：双解调模式AM收音机
公开(公告)号：US20080267313A1
公开(公告)日：2008-10-30
申请号：US11740159
申请日：2007-04-25
申请人： David Meltzer , Gregory A. Blum , Muralikumar A. Padaparambil
发明人： David Meltzer , Gregory A. Blum , Muralikumar A. Padaparambil
IPC分类号： H03C5/00
CPC分类号： H03D1/22
摘要： Apparatuses and methods for receiving an amplitude modulated signal in one of two modes depending on the quality of the received signal. In a first mode, the amplitude modulated signal is converted directly to a baseband signal. In a second mode, the amplitude modulated signal is converted to an intermediate frequency signal. The present invention advantageously combines direct conversion and image-rejection heterodyne receiver topologies with a relatively large degree of component reuse and relatively few additional components.
摘要翻译：根据接收信号的质量，以两种模式之一接收幅度调制信号的装置和方法。在第一模式中，幅度调制信号被直接转换为基带信号。在第二模式中，幅度调制信号被转换成中频信号。本发明有利地将直接转换和图像抑制外差接收器拓扑与相对较大程度的组件重用和相对较少的附加组件相结合。

4. 发明授权

US07268635B2 Circuits for voltage-controlled ring oscillators and method of generating a periodic signal 失效
标题翻译：用于压控环形振荡器的电路和产生周期信号的方法
公开(公告)号：US07268635B2
公开(公告)日：2007-09-11
申请号：US11119311
申请日：2005-04-29
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03B5/24
CPC分类号： H03K3/0315
摘要： Circuits and methods and for generating oscillator outputs using standard integrated circuit components. The basic circuit generally includes two inverters and a variable capacitor to configure a delay of the circuit input and/or output. The oscillator circuit generally includes a plurality of inverter circuits, at least one of which uses a variable capacitor to adjust a delay between stages, and thereby adjust a frequency of oscillation. Thus, the oscillator outputs may be tuned using a single control voltage. The method generally includes the steps of (1) applying an operating voltage to a ring oscillator comprising a plurality of stages; and (2) applying a control voltage to a variable capacitor coupled to a node between at least two of those stages. The circuits have particular advantage in quadrature oscillators, and may be easily implemented using widely available CMOS technology.
摘要翻译：电路和方法，并使用标准集成电路组件产生振荡器输出。基本电路通常包括两个反相器和可变电容器，以配置电路输入和/或输出的延迟。振荡电路通常包括多个反相器电路，其中至少一个使用可变电容器来调整级之间的延迟，从而调节振荡频率。因此，可以使用单个控制电压来调谐振荡器输出。该方法通常包括以下步骤：（1）将工作电压施加到包括多个级的环形振荡器; 以及（2）将控制电压施加到耦合到这些级中的至少两个级之间的节点的可变电容器。这些电路在正交振荡器中具有特别的优点，并且可以使用广泛可用的CMOS技术容易地实现。

5. 发明授权

US07224180B2 Methods and systems for rise-time improvements in differential signal outputs 失效
标题翻译：差分信号输出上升时间的方法和系统
公开(公告)号：US07224180B2
公开(公告)日：2007-05-29
申请号：US10991724
申请日：2004-11-18
申请人： Michael Hargrove , David Meltzer
发明人： Michael Hargrove , David Meltzer
IPC分类号： H03K17/16 , H03H7/38 , H01P5/12
CPC分类号： H04L25/0278 , H01L23/60 , H01L23/645 , H01L24/48 , H01L24/49 , H01L27/0248 , H01L2223/6611 , H01L2224/48091 , H01L2224/48463 , H01L2224/4911 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/14 , H01L2924/19042 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H03K19/00323 , H03K19/013 , H04L25/0272 , H04L25/028 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A method for maintaining signal integrity of a differential output signal generated from a differential driver is disclosed. The method includes receiving the differential output signal from the differential driver. Once received, the method includes tuning the differential output signal by exposing the differential output signal to an inductance. The inductance is configured to reduce signal mismatch between complementary signals of the differential output signal. The signal mismatch is a result of having each of the complementary signals exposed to different capacitive loading. A device and system is also provided, which include integrating an inductor between the output leads of a differential driver. The inductor is sized for the particular frequency of operation, and the inductor provides an inductance that assists in eliminating mismatch between the complementary signals of the differential output. A reduction and/or elimination of the mismatch will assist in improving the rise-time of the differential signals.
摘要翻译：公开了一种用于维持从差分驱动器产生的差分输出信号的信号完整性的方法。该方法包括从差分驱动器接收差分输出信号。一旦接收到，该方法包括通过将差分输出信号暴露于电感来调谐差分输出信号。电感被配置为减小差分输出信号的互补信号之间的信号失配。信号失配是使每个互补信号暴露于不同的电容负载的结果。还提供了一种设备和系统，其包括在差分驱动器的输出引线之间集成电感器。电感器的尺寸适用于特定的工作频率，电感器提供的电感有助于消除差分输出的互补信号之间的失配。减少和/或消除失配将有助于改善差分信号的上升时间。

6. 发明申请

US20060250198A1 Integrated resonator structure and methods for its manufacture and use 有权
标题翻译：集成谐振器结构及其制造和使用的方法
公开(公告)号：US20060250198A1
公开(公告)日：2006-11-09
申请号：US11125378
申请日：2005-05-09
申请人： David Meltzer , Michael Hargrove
发明人： David Meltzer , Michael Hargrove
IPC分类号： H03H7/01
CPC分类号： H01L28/10 , H01F17/0013 , H03H2001/0064
摘要： An improved integrated LC resonator and methods for making and using the same are disclosed. The resonator includes (i) a first capacitor plate; (ii) an inductor over and in electrical communication with the first capacitor plate; and (iii) a second capacitor plate over and in electrical communication with the inductor. The method of making includes sequentially forming a first capacitor plate, a first dielectric layer thereon, a first via and an inductor, a second dielectric layer on the inductor, and a second via and a second capacitor plate. Each of the capacitor plates and the inductor are generally formed in different integrated circuit layers (for example, different metallization layers). Embodiments of the present invention can advantageously provide an integrated LC resonator tank having: (i) relatively high Q by reducing or minimizing parasitic effects; and (ii) relatively high shielding from the semiconductor substrate.
摘要翻译：公开了一种改进的集成LC谐振器及其制造和使用方法。谐振器包括（i）第一电容器板; （ii）与所述第一电容器板电连接的电感器; 和（iii）在电感器上并与电感器电连通的第二电容器板。制造方法包括依次形成第一电容器板，第一电介质层，第一通孔和电感器，电感器上的第二电介质层，以及第二通孔和第二电容器板。每个电容器板和电感器通常形成在不同的集成电路层（例如，不同的金属化层）中。本发明的实施例可以有利地提供一种集成的LC谐振器箱，其具有：（i）通过减小或最小化寄生效应来实现相对较高的Q; 和（ii）与半导体衬底相对较高的屏蔽。

7. 发明申请

US20060132209A1 CMOS master/slave flip-flop with integrated multiplexor 失效
标题翻译：具有集成多路复用器的CMOS主/从触发器
公开(公告)号：US20060132209A1
公开(公告)日：2006-06-22
申请号：US11016430
申请日：2004-12-17
申请人： David Meltzer , Muralikumar Padaparambil
发明人： David Meltzer , Muralikumar Padaparambil
IPC分类号： H03K3/289
CPC分类号： H03K3/356139
摘要： A CML master-slave latch incorporates logic into its master latching circuitry to incorporate a multiplexing function into the flip-flop. The multiplexing logic makes use of the pull-up loads and current source of the master latching circuitry. In this manner the pull-up loads and current source typically required for a stand-alone multiplexor are eliminated. Subsequently, the size of the present hybrid master-slave latch is smaller and consumes less power than a traditional combination of an independent multiplexor and master-slave latch. Since the master latching circuitry feeds only into the slave latching circuitry, the pull-up loads and the current sources of the master latching circuitry and slave latching circuitry may be optimized separately for achieving faster performance or less power consumption.
摘要翻译： CML主从锁存器将逻辑并入其主锁存电路，以将多路复用功能并入到触发器中。复用逻辑利用主锁存电路的上拉负载和电流源。以这种方式，消除了独立复用器通常需要的上拉负载和电流源。随后，当前的混合主 - 从锁存器的大小比独立多路复用器和主 - 从锁存器的传统组合消耗更少的功率。由于主锁存电路仅馈入从锁存电路，因此可以单独优化主锁存电路和从锁存电路的上拉负载和电流源，以实现更快的性能或更低的功耗。

8. 发明申请

US20060119398A1 Digital frequency difference detector with inherent low pass filtering and lock detection 有权
标题翻译：数字频差检测器，具有固有的低通滤波和锁定检测
公开(公告)号：US20060119398A1
公开(公告)日：2006-06-08
申请号：US11007546
申请日：2004-12-08
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03D13/00
CPC分类号： H03L7/085 , H03D13/002 , H03L7/095
摘要： A structure and method for implementing a fully digital frequency difference detector uses an n-bit counter to count cycles of a reference clock signal and an m-bit counter to count cycles of a synthesized clock signal, where m is greater than n. The two counters operate concurrently, and both are halted when the n-bit counter overflows into its nth bit position. Two latches respectively record if bits n and (n+1) in the m-bit become set prior to the n-bit counter overflowing. By observing the state of the two latches and the state of a predefined bit range within the m-counter, the frequency difference detector can determined if the frequency of the synthesized clock is greater than, less than, or locked to the frequency of the reference clock signal.
摘要翻译：用于实现全数字频差检测器的结构和方法使用n位计数器对参考时钟信号和m位计数器的周期进行计数，以计数合成时钟信号的周期，其中m大于n。两个计数器同时运行，当n位计数器溢出到其第n个位位置时，两个计数器都停止。两个锁存器分别记录在n位计数器溢出之前m位中的位n和（n + 1）是否被置位。通过观察两个锁存器的状态和m个计数器内的预定义位范围的状态，频率差检测器可以确定合成时钟的频率是否大于，小于或锁定到参考的频率时钟信号。

9. 发明申请

US20050242843A1 Differential current mode phase/frequency detector circuit 失效
标题翻译：差分电流模式相位/频率检测电路
公开(公告)号：US20050242843A1
公开(公告)日：2005-11-03
申请号：US10833397
申请日：2004-04-28
申请人： David Meltzer , Muralikumar Padaparambil , Tat Wu
发明人： David Meltzer , Muralikumar Padaparambil , Tat Wu
IPC分类号： H03K5/26 , H03D13/00 , H03L7/089 , H03K19/003
CPC分类号： H03D13/004
摘要： A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.
摘要翻译：全差分相位和频率检测器利用多功能差分逻辑门来实现差分和门操作，并提供完全差分D触发器。多功能差分逻辑门有四个输入，可以分为两对真和补两个信号。通过选择性地将输入重新分配给不同的信号对，可以使差分逻辑门提供同时的与/或非逻辑运算或同时的OR / NOR逻辑运算之一。差分D-触发器按照主/从配置实现，并且响应于输入时钟信号，输入复位输入和输入数据信号的真实和补码形式，并且还提供输出的真实和补充形式信号。相位和频率检测器中的所有组件都以CML电路配置为例。

10. 发明授权

US06604191B1 Method and apparatus for accelerating instruction fetching for a processor 失效
标题翻译：用于加速处理器的指令获取的方法和装置
公开(公告)号：US06604191B1
公开(公告)日：2003-08-05
申请号：US09498932
申请日：2000-02-04
申请人： Brian King Flacks , David Meltzer , Joel Abraham Silberman
发明人： Brian King Flacks , David Meltzer , Joel Abraham Silberman
IPC分类号： G06F1200
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3804 , G06F12/0875
摘要： An instruction fetching system (and/or architecture) which may be utilized by a high-frequency short-pipeline microprocessor, for efficient fetching of both in-line and target instructions. The system contains an instruction fetching unit (IFU), having a control logic and associated components for controlling a specially designed instruction cache (I-cache). The I-cache is a sum-address cache, i.e., it receives two address inputs, which compiled by a decoder to provide the address of the line of instructions desired fetch. The I-cache is designed with an array of cache lines that can contain 32 instructions, and three buffers that each have a capacity of 32 instructions. The three buffers include a Predicted (PRED) buffer that holds the instructions which are currently being executed, a NEXT buffer that holds the instructions which are to be executed after the instructions in the PRED buffer, and an ALT buffer that holds the alternate set of instructions when a branch is predicted taken/not taken and is utilized along with the PRED buffer to permit branch target retrieval within I-cache prior to a prediction.
摘要翻译：可以由高频短流水线微处理器利用的指令获取系统（和/或架构），用于有效地提取在线和目标指令。该系统包含指令提取单元（IFU），具有用于控制专门设计的指令高速缓存（I-cache）的控制逻辑和相关组件。 I缓存是和地址高速缓存，即它接收两个地址输入，其由解码器编译以提供期望提取的指令行的地址。 I缓存设计有可以包含32个指令的高速缓存行数组，每个缓冲区的容量为32个指令。三个缓冲器包括保存当前正在执行的指令的预测（PRED）缓冲器，保存在PRED缓冲器中的指令之后要执行的指令的NEXT缓冲器，以及保存该替换组的ALT缓冲器预测采取/未采取分支时使用指令，并与PRED缓冲区一起使用，以允许在预测之前在I缓存中进行分支目标检索。

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