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1. 发明申请

US20080007272A1 ON-CHIP DETECTION OF POWER SUPPLY VULNERABILITIES 有权
公开(公告)号：US20080007272A1
公开(公告)日：2008-01-10
申请号：US11056822
申请日：2005-02-10
申请人： Frank Ferraiolo , Anuja Sehgal , Peilin Song , Michael Sperling
发明人： Frank Ferraiolo , Anuja Sehgal , Peilin Song , Michael Sperling
IPC分类号： G01R27/28
CPC分类号： G01R31/30 , G01R31/2884 , G01R31/3016 , G01R31/31721
摘要： On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outside a user-defined threshold are detected. The undershoots and overshoots are indicated by a relative difference in phase of the two delay chains. The two delay chains are programmable to detect various frequencies.

2. 发明申请

US20060181324A1 Programmable delay element 有权
标题翻译：可编程延迟元件
公开(公告)号：US20060181324A1
公开(公告)日：2006-08-17
申请号：US11215416
申请日：2005-08-30
申请人： Daniel Dreps , Frank Ferraiolo , Daniel Friedman , Seongwon Kim , Hector Saenz , Michael Sperling
发明人： Daniel Dreps , Frank Ferraiolo , Daniel Friedman , Seongwon Kim , Hector Saenz , Michael Sperling
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , H03K5/133 , H03K2005/00039
摘要： Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.
摘要翻译：公开了具有无毛刺操作的延迟元件和延迟线。作为示例，用于延迟输入信号的装置包括用于产生恒定电流的参考电流发生器，其中恒定电流对电源电压的变化不敏感，耦合到参考电流发生器的至少一个可变偏置电压发生器用于基于由参考电流发生器和数字可编程延迟控制输入产生的恒定电流产生一组偏置电压，以及耦合到所述至少一个可变偏置电压发生器的至少一个延迟元件，用于将输入信号延迟常数由所述至少一个可变偏置电压发生器产生的偏置电压组确定的延迟。

3. 发明申请

US20060176096A1 Power supply insensitive delay element 审中-公开
标题翻译：电源不敏感延迟元件
公开(公告)号：US20060176096A1
公开(公告)日：2006-08-10
申请号：US11056798
申请日：2005-02-10
申请人： Daniel Dreps , Frank Ferraiolo , Daniel Friedman , Seongwon Kim , Robert Reese , Hector Saenz , Michael Sperling
发明人： Daniel Dreps , Frank Ferraiolo , Daniel Friedman , Seongwon Kim , Robert Reese , Hector Saenz , Michael Sperling
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00039 , H03K2005/0013
摘要： A power supply voltage insensitive delay element is provided that enables a digital signal to be delayed without variation due to power supply vulnerabilities. Current is limited through the transistors of the delay element using bias voltages produced by a bias voltage generator coupled to the delay element. The bias voltage generator and the delay element are included in a delay line which facilitates the providing of a delay that is insensitive to voltage fluctuations.
摘要翻译：提供了电源电压不敏感延迟元件，其使数字信号由于电源漏洞而被延迟而没有变化。使用由耦合到延迟元件的偏置电压发生器产生的偏置电压，延迟元件的晶体管限制电流。偏置电压发生器和延迟元件包括在延迟线中，这有助于提供对电压波动不敏感的延迟。

4. 发明申请

US20080074998A1 SELF-HEALING CHIP-TO-CHIP INTERFACE 有权
标题翻译：自我加工芯片到芯片接口
公开(公告)号：US20080074998A1
公开(公告)日：2008-03-27
申请号：US11948620
申请日：2007-11-30
申请人： WIREN BECKER , Daniel Dreps , Frank Ferraiolo , Anand Haridass , Robert Reese
发明人： WIREN BECKER , Daniel Dreps , Frank Ferraiolo , Anand Haridass , Robert Reese
IPC分类号： G01R31/08 , G06F11/00
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译：一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。检测用于芯片的信号路径集合内的有缺陷的信号路径。信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径有缺陷的信号路径。

5. 发明申请

US20070288679A1 276-PIN BUFFERED MEMORY MODULE WITH ENHANCED FAULT TOLERANCE AND A PERFORMANCE-OPTIMIZED PIN ASSIGNMENT 失效
标题翻译： 276引脚缓存的存储器模块，具有增强的容错能力和性能优化的引脚分配
公开(公告)号：US20070288679A1
公开(公告)日：2007-12-13
申请号：US11695679
申请日：2007-04-03
申请人： Daniel Dreps , Frank Ferraiolo , Kevin Gower , Roger Rippens
发明人： Daniel Dreps , Frank Ferraiolo , Kevin Gower , Roger Rippens
IPC分类号： G06F13/36 , G06F12/00
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon including a plurality of high-speed bus interface pills arranged on said card for communicating with a plurality of high-speed busses. The high-speed bus interface pins associated with a single high-speed bus are located on one side of the card with respect to a midpoint of the length of the card, thus the pin assignments are defined such that the performance of the DIMM in a system is optimized for high frequency operation.
摘要翻译：双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将打包内存界面。该卡包括至少276个引脚，其构造为包括布置在所述卡上的多个高速总线接口卡，用于与多个高速总线通信。与单个高速总线相关联的高速总线接口引脚相对于卡的长度的中点位于卡的一侧，因此引脚分配被定义为使得DIMM的性能在系统针对高频操作进行了优化。

6. 发明申请

US20080040571A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR BUS CALIBRATION IN A MEMORY SUBSYSTEM 审中-公开
公开(公告)号：US20080040571A1
公开(公告)日：2008-02-14
申请号：US11874996
申请日：2007-10-19
申请人： Frank Ferraiolo , Kevin Gower
发明人： Frank Ferraiolo , Kevin Gower
IPC分类号： G06F13/00
CPC分类号： G06F13/4239
摘要： A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memory bus and provide scrambled data for use in the periodic recalibration.

7. 发明申请

US20070101086A1 System, method and storage medium for deriving clocks in a memory system 失效
标题翻译：用于在存储器系统中导出时钟的系统，方法和存储介质
公开(公告)号：US20070101086A1
公开(公告)日：2007-05-03
申请号：US11263344
申请日：2005-10-31
申请人： Frank Ferraiolo , Kevin Gower , Martin Schmatz
发明人： Frank Ferraiolo , Kevin Gower , Martin Schmatz
IPC分类号： G06F13/00
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A system, method and storage medium for deriving clocks in a memory system. The method includes receiving a reference oscillator clock at a hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译：一种用于在存储器系统中导出时钟的系统，方法和存储介质。该方法包括在集线器装置处接收参考振荡器时钟。集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。以基准时钟频率工作的基本时钟从参考振荡器时钟导出。通过将基本时钟乘以存储器乘法器导出存储器接口时钟。控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。

8. 发明申请

US20060181914A1 Alignment mode selection mechanism for elastic interface 失效
标题翻译：弹性界面对准模式选择机构
公开(公告)号：US20060181914A1
公开(公告)日：2006-08-17
申请号：US11055841
申请日：2005-02-11
申请人： Frank Ferraiolo , Gary Peterson , Robert Reese
发明人： Frank Ferraiolo , Gary Peterson , Robert Reese
IPC分类号： G11C19/00
CPC分类号： G11C19/287 , G06F5/10 , G06F2205/104
摘要： Methods and apparatus are disclosed for aligning received data bits in elastic interface systems. Depending upon which one of several alignment modes is selected, data bits can be loaded into FIFO latches on rising clock edges if the data was sent on rising clock edges, on falling clock edges if the data was sent on falling clock edges, or on the nearest clock edge if minimum latency is desired. Alternatively, data bits can be delayed by one or more bit times before loading into FIFO latches to reduce the elastic interface system's sensitivity to drift. The present invention permits a user to trade off factors related to for latency, drift, and skew by choosing among different alignment modes in an elastic interface system.
摘要翻译：公开了用于在弹性界面系统中对准接收数据位的方法和装置。根据选择的几种对准模式中的哪一种，如果数据在上升时钟沿发送，则数据位可以在上升时钟沿加载到FIFO锁存器中，如果数据在下降时钟沿发送，则在下降时钟沿如果需要最小延迟，则为最近的时钟沿。或者，数据位可以在加载到FIFO锁存器之前延迟一个或多个位时间，以减少弹性接口系统对漂移的敏感度。本发明允许用户通过在弹性接口系统中的不同对准模式之间进行选择来折衷与延迟，漂移和偏斜相关的因素。

9. 发明申请

US20050007145A1 Thevenins receiver 失效
公开(公告)号：US20050007145A1
公开(公告)日：2005-01-13
申请号：US10616845
申请日：2003-07-10
申请人： Daniel Dreps , Frank Ferraiolo , Anand Haridass , Bao Truong
发明人： Daniel Dreps , Frank Ferraiolo , Anand Haridass , Bao Truong
IPC分类号： H03K19/003
CPC分类号： H04L25/0278 , H04L25/0296
摘要： A termination network has multiple resistors forming multiple voltage dividers with a common node. Half of the resistors are coupled to the positive power supply voltage with P channel field effect transistors (PFETs) and the other half are coupled to the negative or ground power supply voltage with N channel FETs (NFETs). Logic signals are used to control the gates of the FETs. By modifying which FETs are ON, the termination network can be selectively controlled to produce various offset levels with the same impedance level. The impedance levels may also be modified while maintaining the same offset level. A delay circuit may be selectively employed to feedback control signals after a selected delay time to adjust the threshold level to dynamically or statically optimize signal reception.

10. 发明授权

US06252443B1 Delay element using a delay locked loop 有权
标题翻译：延迟元件使用延迟锁定环
公开(公告)号：US06252443B1
公开(公告)日：2001-06-26
申请号：US09295157
申请日：1999-04-20
申请人： Jean-Marc Dortu , Albert M. Chu , Frank Ferraiolo
发明人： Jean-Marc Dortu , Albert M. Chu , Frank Ferraiolo
IPC分类号： H03L706
CPC分类号： H03L7/0805 , H03L7/07 , H03L7/0814
摘要： A delay locked loop circuit, in accordance with the invention, includes a delay line for providing a delay through the delay line in accordance with a control signal, the delay line being connected across an input node and an output node. A delay element is connected to the input node, the delay element for providing a predetermined delay value to an input signal from the input node to provide a delayed input signal. A phase comparator is connected to the output node and the delay element for comparing phase differences between an output signal and the delayed input signal and for outputting the control signal to the delay line such that the delay line provides the predetermined delay value to the delay line across the input and output nodes.
摘要翻译：根据本发明的延迟锁定环路电路包括延迟线，用于根据控制信号通过延迟线提供延迟，延迟线跨输入节点和输出节点连接。延迟元件连接到输入节点，延迟元件用于向来自输入节点的输入信号提供预定的延迟值，以提供延迟的输入信号。相位比较器连接到输出节点和延迟元件，用于比较输出信号和延迟输入信号之间的相位差，并将控制信号输出到延迟线，使得延迟线向延迟线提供预定的延迟值跨输入和输出节点。

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