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1. 发明授权

US5970439A Performance monitoring in a data processing system 失效
标题翻译：数据处理系统中的性能监控
公开(公告)号：US5970439A
公开(公告)日：1999-10-19
申请号：US816626
申请日：1997-03-13
申请人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon , Jack Chris Randolph
发明人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon , Jack Chris Randolph
IPC分类号： G06F11/34 , G06F12/00
CPC分类号： G06F11/3409 , G06F11/348 , G06F2201/81 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： Performance monitoring capabilities are expanded to an entire data processing system so that performance analyses can be made for operations occurring within the entire data processing system and not merely within the processor or any other device containing the performance monitor. Therefore, there is a provision for communicating performance monitor-related signals between the various performance monitors within the various devices and processor within a data processing system.
摘要翻译：性能监控功能扩展到整个数据处理系统，以便可以对整个数据处理系统中发生的操作进行性能分析，而不仅仅是处理器或包含性能监视器的任何其他设备。因此，存在用于在数据处理系统内的各种设备和处理器内的各种性能监视器之间传送性能监视器相关信号的规定。

2. 发明授权

US5862371A Method and system for instruction trace reconstruction utilizing performance monitor outputs and bus monitoring 失效
标题翻译：使用性能监视器输出和总线监控的指令轨迹重建方法和系统
公开(公告)号：US5862371A
公开(公告)日：1999-01-19
申请号：US758198
申请日：1996-11-25
申请人： Frank Eliot Levine , William John Starke , Edward Hugh Welbon , Jack Chris Randolph
发明人： Frank Eliot Levine , William John Starke , Edward Hugh Welbon , Jack Chris Randolph
IPC分类号： G06F11/34 , G06F11/36 , G06F9/00
CPC分类号： G06F11/3636 , G06F11/3466 , G06F11/349 , G06F2201/885
摘要： A method and system for instruction trace reconstruction utilizing performance monitor outputs and bus monitoring. Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyzes and timing. One well known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine instruction addresses, data addresses and data during the trace, if the initial architectural state of the system is known. The difficulty in reconstructing an instruction trace from monitored bus traffic can be decreased substantially if more definitive information regarding the actual instruction sequence can be obtained. To this end, an internal performance monitor within the processor system is utilized to generate an output each processor clock cycle which is indicative of the exact number of instructions which were executed during that clock cycle, an indication of whether or not a branch instruction was taken or not taken, an offset for each interrupt vector which has been taken, the number of data cache misses, the number of instruction cache misses, the number of store conditional instructions which were executed and the number of store conditional instructions which failed. This information, in combination with monitored bus traffic may be utilized to efficiently and accurately reconstruct an instruction trace without adversely affecting performance of the system under test.
摘要翻译：一种使用性能监视器输出和总线监控的指令轨迹重建方法和系统。处理器系统和内存子系统的性能预测对于正确了解系统内的工作负载非常重要。通常使用指令轨迹来确定指令的分配，寄存器依赖性的识别，分支路径分析和定时。如果系统的初始架构状态已知，则可以通过监视总线流量来确定跟踪期间的指令地址，数据地址和数据，来实现重建指令轨迹的一种众所周知的技术。如果可以获得关于实际指令序列的更确定的信息，则可以显着地减少从监视的总线业务重建指令轨迹的困难。为此，使用处理器系统内的内部性能监视器来产生每个处理器时钟周期的输出，其指示在该时钟周期期间执行的指令的精确数量，是否采用分支指令或不采取，已经采取的每个中断向量的偏移，数据高速缓存未命中的数量，指令高速缓存未命中的数量，被执行的存储条件指令的数量和存储条件指令的数量失败。可以将该信息与监视的总线业务相结合，以有效且准确地重建指令轨迹，而不会不利地影响被测系统的性能。

3. 发明授权

US5961654A Operand fetch bandwidth analysis 失效
标题翻译：操作数获取带宽分析
公开(公告)号：US5961654A
公开(公告)日：1999-10-05
申请号：US767706
申请日：1996-12-17
申请人： Frank Eliot Levine , Roy Stuart Moore , Charles Philip Roth , Edward Hugh Welbon
发明人： Frank Eliot Levine , Roy Stuart Moore , Charles Philip Roth , Edward Hugh Welbon
IPC分类号： G06F11/34 , G06F11/30
CPC分类号： G06F11/3409 , G06F11/3452 , G06F11/348 , G06F2201/81 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
摘要翻译：实现多个计数器的性能监视器计数几个事件以提供指令获取带宽分析，每个指令的周期（CPI）无限和有限分析，操作数获取带宽分析，指令并行性分析和后沿分析。对数据处理系统的性能执行这样的分析，以便设计者可以开发改进的处理器架构。

4. 发明授权

US5881306A Instruction fetch bandwidth analysis 失效
标题翻译：指令提取带宽分析
公开(公告)号：US5881306A
公开(公告)日：1999-03-09
申请号：US767705
申请日：1996-12-17
申请人： Frank Eliot Levine , Roy Stuart Moore , Charles Philip Roth , Edward Hugh Welbon
发明人： Frank Eliot Levine , Roy Stuart Moore , Charles Philip Roth , Edward Hugh Welbon
IPC分类号： G06F11/34 , G06F15/00
CPC分类号： G06F11/3409 , G06F11/348 , G06F2201/81 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
摘要翻译：实现多个计数器的性能监视器计数几个事件以提供指令获取带宽分析，每个指令的周期（CPI）无限和有限分析，操作数获取带宽分析，指令并行性分析和后沿分析。对数据处理系统的性能执行这样的分析，以便设计者可以开发改进的处理器架构。

5. 发明授权

US5751945A Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system 失效
标题翻译：用于性能监控的方法和系统停止，以识别处理系统中的管道瓶颈和停顿
公开(公告)号：US5751945A
公开(公告)日：1998-05-12
申请号：US538102
申请日：1995-10-02
申请人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
发明人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
IPC分类号： G06F11/34 , G06F11/00
CPC分类号： G06F11/348 , G06F11/3409 , G06F11/3423 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method for identifying bottlenecks within a processing system, the processing system including a plurality of performance monitor counters (PMCs) and at least one monitor mode control register (MMCR) to configure the operations of at least one of the PMCs, includes, for a predetermined sampling period, counting a number of cycles that a dispatch unit is stalled, counting a number of cycles that each of a plurality of execution units is stalled, counting a number of cycles that a load/store unit is stalled, and counting a number of cycles that a completion unit is stalled. The counting in the units is performed to identify the relative effect of stalls occurring within each unit during processing to produce an overview of relative effect of the stalling of each unit on the total system bottleneck conditions.
摘要翻译：一种用于识别处理系统内的瓶颈的方法，所述处理系统包括多个性能监视计数器（PMC）和至少一个监视模式控制寄存器（MMCR），用于配置至少一个所述PMC的操作，对分配单元停止的周期数进行计数，对多个执行单元中的每个执行单元停止的周期数进行计数，对加载/存储单元停止的周期数进行计数，并对数量进行计数的完成单位停滞的周期。执行单元中的计数以识别在处理期间在每个单元内发生的失速的相对影响，以产生每个单元的停止对总系统瓶颈条件的相对影响的概述。

6. 发明授权

US06189072B1 Performance monitoring of cache misses and instructions completed for instruction parallelism analysis 失效
标题翻译：高速缓存未命中的性能监视和指令并行性分析完成的指令
公开(公告)号：US06189072B1
公开(公告)日：2001-02-13
申请号：US08767656
申请日：1996-12-17
申请人： Frank Eliot Levine , Roy Stuart Moore , Charles Philip Roth , Edward Hugh Welbon
发明人： Frank Eliot Levine , Roy Stuart Moore , Charles Philip Roth , Edward Hugh Welbon
IPC分类号： G06F1210
CPC分类号： G06F11/3409 , G06F2201/81 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
摘要翻译：实现多个计数器的性能监视器计数几个事件以提供指令获取带宽分析，每个指令的周期（CPI）无限和有限分析，操作数获取带宽分析，指令并行性分析和后沿分析。对数据处理系统的性能执行这样的分析，以便设计者可以开发改进的处理器架构。

7. 发明授权

US6067644A System and method monitoring instruction progress within a processor 失效
标题翻译：处理器内的系统和方法监视指令进度
公开(公告)号：US6067644A
公开(公告)日：2000-05-23
申请号：US59736
申请日：1998-04-15
申请人： Frank Eliot Levine , Roy Stuart Moore , Charles Philip Roth , Edward Hugh Welbon
发明人： Frank Eliot Levine , Roy Stuart Moore , Charles Philip Roth , Edward Hugh Welbon
IPC分类号： G06F9/38 , G06F11/34 , G06F11/00
CPC分类号： G06F9/3865 , G06F11/348 , G06F9/3824 , G06F9/3867 , G06F2201/81 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A processor operable for processing an instruction through a plurality of internal stages will produce a result of the processing of the process at each stage or a reason code why the stage was unable to process the instruction. The result or the reason code will then be passed to a subsequent stage, which will attempt to process the instruction. The second stage will forward the reason code when it cannot produce its own result and it is idle. The second stage will create its own reason code when it is not idle but cannot produce a result, and will forward this reason code.
摘要翻译：可操作用于通过多个内部级处理指令的处理器将产生处理每个阶段的过程的结果或为什么阶段不能处理该指令的原因代码。然后，结果或原因代码将被传递到后续阶段，该阶段将尝试处理该指令。第二阶段将在原因代码无法产生自己的结果并且空闲时转发。第二阶段将在空闲时创建自己的原因代码，但不能产生结果，并将转发此原因代码。

8. 发明授权

US5949971A Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system 失效
标题翻译：通过识别处理系统中序列化指令执行时间的频率和时间长度来进行性能监控的方法和系统
公开(公告)号：US5949971A
公开(公告)日：1999-09-07
申请号：US537586
申请日：1995-10-02
申请人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
发明人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
IPC分类号： G06F11/34 , G06F11/30
CPC分类号： G06F11/3419 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method and system for identifying frequency and length of time of execution of serialization instructions in a pipeline of a processing system, the processing including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least PMCs, includes counting a number of instructions forcing serialization or logically requiring serialization of the pipeline during a predetermined sampling period. Further included are counting a number of additional cycles required to complete the instructions during the predetermined sampling period, and determining a loss of efficiency from the counted number of instructions and the counted number of additional cycles accumulated during the predetermined sampling period.
摘要翻译：一种用于识别在处理系统的流水线中执行串行化指令的时间的频率和长度的方法和系统，所述处理包括至少一个性能监视计数器（PMC）和至少一个监视模式控制寄存器（MMCR），以配置所述至少PMC的操作包括在预定采样周期内计数强制串行化或逻辑地要求对流水线进行串行化的指令。还包括计数在预定采样周期内完成指令所需的附加周期数，以及根据计数的指令数和在预定采样周期期间累积的附加周期的计数次数来确定效率损失。

9. 发明授权

US5938760A System and method for performance monitoring of instructions in a re-order buffer 失效
标题翻译：用于在重新排序缓冲器中执行指令的性能监视的系统和方法
公开(公告)号：US5938760A
公开(公告)日：1999-08-17
申请号：US767655
申请日：1996-12-17
申请人： Frank Eliot Levine , Roy Stuart Moore , Charles Philip Roth , Edward Hugh Welbon
发明人： Frank Eliot Levine , Roy Stuart Moore , Charles Philip Roth , Edward Hugh Welbon
IPC分类号： G06F11/34 , G06F11/28
CPC分类号： G06F11/3409 , G06F2201/81 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
摘要翻译：实现多个计数器的性能监视器计数几个事件以提供指令获取带宽分析，每个指令的周期（CPI）无限和有限分析，操作数获取带宽分析，指令并行性分析和后沿分析。对数据处理系统的性能执行这样的分析，以便设计者可以开发改进的处理器架构。

10. 发明授权

US5835702A Performance monitor 失效
标题翻译：性能监视器
公开(公告)号：US5835702A
公开(公告)日：1998-11-10
申请号：US734335
申请日：1996-10-21
申请人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
发明人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
IPC分类号： G06F11/34 , G01B21/00
CPC分类号： G06F11/3409 , G06F11/348 , G06F2201/81 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method and system for performing performance monitoring within a data processing system whereby a counting function to be performed by a particular counter within the performance monitor is dependent upon a particular event programmed within another counter within the performance monitor so that reprogramming of all code points for each performance counter is not required.
摘要翻译：一种用于在数据处理系统内执行性能监视的方法和系统，由此由性能监视器内的特定计数器执行的计数功能取决于在性能监视器内的另一个计数器内编程的特定事件，从而重新编程所有代码点，以便每个性能计数器都不是必需的。

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