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1. 发明授权

US08413088B1 Verification plans to merging design verification metrics 有权
标题翻译：合并设计验证指标的验证计划
公开(公告)号：US08413088B1
公开(公告)日：2013-04-02
申请号：US12426188
申请日：2009-04-17
申请人： Frank Armbruster , Sandeep Pagey , F. Erich Marschner , Dan Leibovich , Alok Jain , Axel Scherer , Yaron Peri-Glass
发明人： Frank Armbruster , Sandeep Pagey , F. Erich Marschner , Dan Leibovich , Alok Jain , Axel Scherer , Yaron Peri-Glass
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/2848 , G06F17/504
摘要： A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment on the invention, a plurality of verification scopes of an integrated circuit design as defined as part of a verification plan. A plurality of verification runs are executed within two or more verification scopes defined by the verification plan. At least two verification runs are selected to merge verification results together. Like named scenarios are merged together for each verification scope to generate merged verification results that are then stored into a merge database. A verification report is generated for the integrated circuit design from the merged verification results. A merge point may be specified so like named subtrees and subgroups may be merged across different verification scopes of selected verification runs. The merge point may combine check and coverage results obtained during simulation with check and coverage results obtained during formal verification.
摘要翻译：提供了一种用于产生数字电路验证的方法和装置。在本发明的示例性实施例中，定义为验证计划的一部分的集成电路设计的多个验证范围。在由验证计划定义的两个或多个验证范围内执行多个验证运行。选择至少两次验证运行以将验证结果合并在一起。对于每个验证范围，像命名方案一样合并生成合并的验证结果，然后将其存储到合并数据库中。从合并的验证结果生成集成电路设计的验证报告。可以指定合并点，以便命名子树和子组可以在所选验证运行的不同验证范围之间合并。合并点可以将在模拟期间获得的检查和覆盖结果与在正式验证期间获得的检查和覆盖结果相结合。

2. 发明授权

US08560985B1 Configuration-based merging of coverage data results for functional verification of integrated circuits 有权
标题翻译：覆盖数据结构的配置合并，用于集成电路的功能验证
公开(公告)号：US08560985B1
公开(公告)日：2013-10-15
申请号：US13226481
申请日：2011-09-06
申请人： Bijaya Sahu , Sandeep Pagey , Frank Armbruster , Hannes Froehlich
发明人： Bijaya Sahu , Sandeep Pagey , Frank Armbruster , Hannes Froehlich
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/2848 , G06F17/504
摘要： In one embodiment of the invention, a method for verification of an integrated circuit design is disclosed. The method includes independently executing simulation runs in response to a plurality of coverage models to respectively generate a plurality of coverage data for a plurality of functional blocks within one or more integrated circuit designs; generating a target coverage model to selectively merge at least first coverage data associated with a first coverage model and second coverage data associated with a second coverage model; and in response to the target coverage model and the plurality of simulation runs, selectively projecting the plurality of coverage data into a merged coverage data result associated with the target coverage model. The method may further store the merged coverage data results into a storage device. The plurality of simulation runs may include at least one functional simulation run and at least one formal verification run.
摘要翻译：在本发明的一个实施例中，公开了用于验证集成电路设计的方法。该方法包括响应于多个覆盖模型独立地执行仿真运行，以分别在一个或多个集成电路设计内生成多个功能块的多个覆盖数据; 生成目标覆盖模型以选择性地合并与第一覆盖模型相关联的至少第一覆盖数据和与第二覆盖模型相关联的第二覆盖数据; 并且响应于所述目标覆盖模型和所述多个模拟运行，选择性地将所述多个覆盖数据投影到与所述目标覆盖模型相关联的合并覆盖数据结果中。该方法还可以将合并的覆盖数据结果存储到存储设备中。多个模拟运行可以包括至少一个功能模拟运行和至少一个正式验证运行。

3. 发明授权

US09098637B1 Ranking process for simulation-based functional verification 有权
标题翻译：基于模拟功能验证的排名流程
公开(公告)号：US09098637B1
公开(公告)日：2015-08-04
申请号：US13278930
申请日：2011-10-21
申请人： Bijaya Kumar Sahu , Frank Armbruster , Hannes Froehlich , Sandeep Pagey
发明人： Bijaya Kumar Sahu , Frank Armbruster , Hannes Froehlich , Sandeep Pagey
IPC分类号： G06F17/50 , G06F11/36
CPC分类号： G06F11/3692 , G06F11/261 , G06F11/263 , G06F11/3688
摘要： The present disclosure relates to a method for verifying a digital design using a computing device. The method may include determining one or more tests associated with verifying the digital design and generating, using the computing device, a verification result by performing one or more verification runs on the digital design. The method may further include merging coverage data generated by the one or more verification runs and ranking the one or more tests based upon, at least in part, a first verification run having a first configuration and a second verification run having a second configuration, wherein the first and second configurations differ.
摘要翻译：本公开涉及一种使用计算设备验证数字设计的方法。该方法可以包括确定与验证数字设计相关联的一个或多个测试，并且通过在数字设计上执行一个或多个验证运行来使用计算设备生成验证结果。该方法还可以包括合并由一个或多个验证运行产生的覆盖数据，并且至少部分地基于具有第一配置的第一验证运行和具有第二配置的第二验证运行来对一个或多个测试进行排序，其中第一和第二配置不同。

4. 发明授权

US07353159B2 Method for parallel simulation on a single microprocessor using meta-models 有权
标题翻译：使用元模型对单个微处理器进行并行仿真的方法
公开(公告)号：US07353159B2
公开(公告)日：2008-04-01
申请号：US10146331
申请日：2002-05-15
申请人： Frank Armbruster , Bodo Eberhard Hoppe , Johannes Koesters , Klaus-Dieter Schubert
发明人： Frank Armbruster , Bodo Eberhard Hoppe , Johannes Koesters , Klaus-Dieter Schubert
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention generally relates to hardware development and design, and in particular it relates to a method for simulating hardware. A meta model (22) is compiled for integrating a plurality of n different instantiations (12A, . . . 12N) of the same hardware model, and facilities and signals of different instantiations are resolved by instantiation-specific name space specifications in a code switch (24,26). Thus, computing time is saved because by simulating the meta model, the processor resources, for instance, storage spaces, are utilized more efficiently.
摘要翻译：本发明一般涉及硬件开发和设计，特别涉及一种用于模拟硬件的方法。编辑元模型（22）用于集成相同硬件模型的多个n个不同实例（12A，...，12N），并且不同实例的设施和信号通过实例化特定名称空间规范来解析代码开关（24,26）。因此，通过模拟元模型，节省了计算时间，更有效地利用处理器资源，例如存储空间。

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