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2. 发明授权

US5773350A Method for forming a self-aligned bipolar junction transistor with silicide extrinsic base contacts and selective epitaxial grown intrinsic base 失效
标题翻译：用硅化物外部基极触点和选择性外延生长的本征基底形成自对准双极结晶体管的方法
公开(公告)号：US5773350A
公开(公告)日：1998-06-30
申请号：US891451
申请日：1997-07-10
申请人： Francois Herbert , Rashid Bashir
发明人： Francois Herbert , Rashid Bashir
IPC分类号： H01L21/331 , H01L29/732 , H01L21/301
CPC分类号： H01L29/7378 , H01L29/66287 , H01L29/732 , Y10S148/01
摘要： In a method of fabricating a self-aligned bipolar junction transistor with silicide extrinsic base contacts and selective epitaxial grown intrinsic base region, the sinker and buried N+ layer regions are formed in a semiconductor substrate with trench oxide isolation. Thin oxide is then formed on the structure. Next, metal silicide is deposited on the thin oxide and p-dopant implanted into the silicide. LTO is then deposited on the doped silicide followed by deposition of nitride. Next, the nitride, LTO and silicide layers are etched, stopping on the thin oxide layer. The thin oxide is then etched to expose the silicon. The etch undercuts the thin oxide under the nitride. A thin p+ epitaxial base is then selectively grown on the silicon and the metal silicide only. The base can be silicon or a silicon germanium layer to form a heterojunction transistor. Next, thin LTO is deposited followed by deposition of nitride. An RIE of the nitride is then performed to form nitride spacers, stopping on the thin LTO. The thin LTO is then wet etched to open the epitaxial base. A n-type, low-doped, selective single crystalline silicon emitter is then grown. This is followed by deposition of polysilicon and an n-dopant implant into the polysilicon. The polysilicon is then masked and etched to define a n+ polysilicon region in contact with the n-type single crystalline emitter. Next, a layer of oxide is deposited, followed by a furnace drive and rapid thermal anneal activation step for the base and emitter. Base, emitter and collector vias are opened and a metallization layer is formed and patterned to provide base, emitter and collector contacts.
摘要翻译：在制造具有硅化物本征基极触点和选择性外延生长的本征基极区域的自对准双极结型晶体管的方法中，沉积片和埋入的N +层区域形成在具有沟槽氧化物隔离的半导体衬底中。然后在结构上形成薄氧化物。接下来，将金属硅化物沉积在硅化物中的薄氧化物和p掺杂剂上。然后将LTO沉积在掺杂的硅化物上，随后沉积氮化物。接下来，蚀刻氮化物，LTO和硅化物层，停止在薄氧化物层上。然后蚀刻薄氧化物以暴露硅。蚀刻在氮化物之下切割薄氧化物。然后，在硅和金属硅化物上选择性地生长薄的p +外延基底。基底可以是硅或硅锗层以形成异质结晶体管。接下来，沉积薄的LTO，随后沉积氮化物。然后执行氮化物的RIE以形成氮化物间隔物，停止在薄LTO上。然后将薄的LTO湿式蚀刻以打开外延基底。然后生长n型，低掺杂，选择性单晶硅发射体。随后将多晶硅和n掺杂剂注入沉积到多晶硅中。然后对多晶硅进行掩模蚀刻以限定与n型单晶发射体接触的n +多晶硅区域。接下来，沉积一层氧化物，然后进行炉驱动和用于基极和发射极的快速热退火激活步骤。打开基极，发射极和集电极通孔，并形成金属化层并构图以提供基极，发射极和集电极触点。

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