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1. 发明申请

US20090269878A1 EMBEDDED WAVEGUIDE DETECTORS 审中-公开
标题翻译：嵌入式波形检测器
公开(公告)号：US20090269878A1
公开(公告)日：2009-10-29
申请号：US12420558
申请日：2009-04-08
申请人： Francisco A. Leon , Lawrence C. West , Yuichi Wada , Gregory L. Wojcik , Stephen Moffatt
发明人： Francisco A. Leon , Lawrence C. West , Yuichi Wada , Gregory L. Wojcik , Stephen Moffatt
IPC分类号： H01L21/20
CPC分类号： G02B6/12004 , G02B2006/12061 , H01L31/0232 , H01L31/0288 , H01L31/105 , H01L31/1812 , Y02E10/50
摘要： A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.
摘要翻译：一种制造检测器的方法，包括：在衬底中形成沟槽，所述衬底具有上表面; 在所述衬底和所述沟槽中形成第一掺杂半导体层; 在所述第一掺杂半导体层上形成第二半导体层并延伸到所述沟槽中，所述第二半导体层的导电率小于所述第一掺杂半导体层的导电性; 在所述第二半导体层上形成第三掺杂半导体层并延伸到所述沟槽中; 去除在由衬底的表面限定的平面之上的第一层，第二层和第三层的部分，以产生上部基本平坦的表面，并且暴露沟槽中的第一掺杂半导体层的上端; 形成第一电接触到第一半导体掺杂层; 以及向所述第三半导体掺杂层形成第二电接触。

2. 发明授权

US07075165B2 Embedded waveguide detectors 失效
标题翻译：嵌入式波导检测器
公开(公告)号：US07075165B2
公开(公告)日：2006-07-11
申请号：US10856750
申请日：2004-05-28
申请人： Francisco A. Leon , Lawrence C. West , Yuichi Wada , Gregory L. Wojcik , Stephen Moffatt
发明人： Francisco A. Leon , Lawrence C. West , Yuichi Wada , Gregory L. Wojcik , Stephen Moffatt
IPC分类号： H01L31/075
CPC分类号： G02B6/12004 , G02B2006/12061 , H01L31/0232 , H01L31/0288 , H01L31/105 , H01L31/1812 , Y02E10/50
摘要： A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.
摘要翻译：一种制造检测器的方法，包括：在衬底中形成沟槽，所述衬底具有上表面; 在所述衬底和所述沟槽中形成第一掺杂半导体层; 在所述第一掺杂半导体层上形成第二半导体层并延伸到所述沟槽中，所述第二半导体层的导电率小于所述第一掺杂半导体层的导电性; 在所述第二半导体层上形成第三掺杂半导体层并延伸到所述沟槽中; 去除在由衬底的表面限定的平面之上的第一层，第二层和第三层的部分，以产生上部基本平坦的表面，并且暴露沟槽中的第一掺杂半导体层的上端; 形成第一电接触到第一半导体掺杂层; 以及向所述第三半导体掺杂层形成第二电接触。

3. 发明授权

US07001788B2 Maskless fabrication of waveguide mirrors 失效
标题翻译：波导镜无掩模制造
公开(公告)号：US07001788B2
公开(公告)日：2006-02-21
申请号：US10858524
申请日：2004-05-28
申请人： Francisco A. Leon , Lawrence C. West , Gregory L. Wojcik , Yuichi Wada
发明人： Francisco A. Leon , Lawrence C. West , Gregory L. Wojcik , Yuichi Wada
IPC分类号： H01L21/00
CPC分类号： G02B6/12004 , G02B6/122 , G02B6/132 , G02B6/136 , G02B2006/121 , G02B2006/12104
摘要： A method of fabricating a waveguide mirror that involves etching a trench in a silicon substrate; depositing a film (e.g. silicon dioxide) over the surface of the silicon substrate and into the trench; ion etching the film to remove at least some of the deposited silicon dioxide and to leave a facet of film in inside corners of the trench; depositing a layer of SiGe over the substrate to fill up the trench; and planarizing the deposited SiGe to remove the SiGe from above the level of the trench.
摘要翻译：一种制造波导反射镜的方法，涉及蚀刻硅衬底中的沟槽; 在硅衬底的表面上沉积膜（例如二氧化硅）并进入沟槽; 离子蚀刻膜以去除沉积的二氧化硅中的至少一些并且在沟槽的内部角落留下膜的小面; 在衬底上沉积一层SiGe以填充沟槽; 并且平坦化沉积的SiGe以从沟槽的高度上方除去SiGe。

4. 发明授权

US07760980B2 Ridge technique for fabricating an optical detector and an optical waveguide 失效
标题翻译：用于制造光学检测器和光波导的脊技术
公开(公告)号：US07760980B2
公开(公告)日：2010-07-20
申请号：US11514291
申请日：2006-08-31
申请人： Lawrence C. West , Gregory L. Wojcik , Francisco A. Leon , Yonah Cho , Andreas Goebel
发明人： Lawrence C. West , Gregory L. Wojcik , Francisco A. Leon , Yonah Cho , Andreas Goebel
IPC分类号： G02B6/10 , G02B6/13
CPC分类号： G02B6/132 , G02B6/12004 , G02B6/1347 , G02B6/136 , G02B2006/12097 , G02B2006/121 , G02B2006/12123 , G02B2006/12176 , H01L31/02327 , H01L31/1812 , Y02E10/50
摘要： A method of fabricating on a substrate an optical detector in an optical waveguide, the method involving: forming at least one layer on a surface of the substrate, said at least one layer comprising SiGe; implanting an impurity into the at least one layer over a first area to form a detector region for the optical detector; etching into the at least one layer in a first region and a second region to form a ridge between the first and second regions, said ridge defining the optical detector and the optical waveguide; filling the first and second regions with a dielectric material having a lower refractive index than SiGe; and after filling the first and second regions with the dielectric material, removing surface material to form a planarized upper surface.
摘要翻译：一种在光波导中在基板上制造光检测器的方法，所述方法包括：在所述基板的表面上形成至少一层，所述至少一层包括SiGe; 在第一区域上将杂质注入到所述至少一个层中以形成用于所述光学检测器的检测器区域; 在第一区域和第二区域中蚀刻到所述至少一个层中以在所述第一和第二区域之间形成脊，所述脊限定所述光学检测器和所述光波导; 用具有比SiGe低的折射率的电介质材料填充第一和第二区域; 并且在用电介质材料填充第一和第二区域之后，去除表面材料以形成平坦化的上表面。

5. 发明授权

US07151881B2 Impurity-based waveguide detectors 失效
标题翻译：基于杂质的波导检测器
公开(公告)号：US07151881B2
公开(公告)日：2006-12-19
申请号：US10856127
申请日：2004-05-28
申请人： Lawrence C. West , Thomas P. Pearsall , Francisco A. Leon , Stephen Moffatt
发明人： Lawrence C. West , Thomas P. Pearsall , Francisco A. Leon , Stephen Moffatt
IPC分类号： G02B6/10
CPC分类号： G02B6/42 , G02B6/136 , G02B2006/12123 , H01L31/02327 , H01L31/0312 , H01L31/09 , H01L31/105 , H01L31/1105 , H01L31/1812 , Y02E10/50
摘要： An optical circuit including a semiconductor substrate; an optical waveguide formed in or on the substrate; and an optical detector formed in or on the semiconductor substrate, wherein the optical detector is aligned with the optical waveguide so as to receive an optical signal from the optical waveguide during operation, and wherein the optical detector has: a first electrode; a second electrode; and an intermediate layer between the first and second electrodes, the intermediate layer being made of a semiconductor material characterized by a conduction band, a valence band, and deep level energy states introduced between the conduction and valence bands.
摘要翻译：一种包括半导体衬底的光学电路; 形成在基板中或基板上的光波导; 以及形成在所述半导体衬底中或之上的光学检测器，其中所述光学检测器与所述光波导对准，以便在操作期间从所述光波导接收光信号，并且其中所述光学检测器具有：第一电极; 第二电极; 以及在所述第一和第二电极之间的中间层，所述中间层由导电带和导带之间引入的导带，价带和深能级状态的半导体材料制成。

6. 发明授权

US07205624B2 Self-aligned implanted waveguide detector 失效
标题翻译：自对准植入波导检测器
公开(公告)号：US07205624B2
公开(公告)日：2007-04-17
申请号：US10959897
申请日：2004-10-06
申请人： Francisco A. Leon , Lawrence C. West
发明人： Francisco A. Leon , Lawrence C. West
IPC分类号： H01L31/00
CPC分类号： H01L31/035254 , B82Y20/00 , G02B6/12004
摘要： A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the first sidewall to form a first conductive region that has a top end that is part of the top end of the island; implanting a second dopant into the second sidewall to form a second conductive region that has a top end that is part of the top end of the island; fabricating a first electrical connection to the top end of the first conductive region; and fabricating a second electrical connection to the top end of the second conductive region.
摘要翻译：一种制造检测器的方法，所述方法包括在衬底上形成检测器芯材料岛，所述岛具有水平取向的顶端，垂直取向的第一侧壁和与所述第一侧壁相对的垂直取向的第二侧壁; 将第一掺杂剂注入到所述第一侧壁中以形成具有作为所述岛的顶端的一部分的顶端的第一导电区域; 将第二掺杂剂注入所述第二侧壁中以形成具有作为所述岛的顶端的一部分的顶端的第二导电区域; 制造到第一导电区域的顶端的第一电连接; 以及制造到所述第二导电区域的顶端的第二电连接。

7. 发明授权

US07101725B2 Solution to thermal budget 失效
标题翻译：热预算解决方案
公开(公告)号：US07101725B2
公开(公告)日：2006-09-05
申请号：US10896754
申请日：2004-07-22
申请人： Yuichi Wada , Francisco A. Leon
发明人： Yuichi Wada , Francisco A. Leon
IPC分类号： H01L21/00
CPC分类号： G02B6/12004 , B82Y20/00 , C30B29/12 , C30B33/00 , G02B6/12 , G02B6/4214 , G02B6/43 , H01L21/84 , H01L27/1203 , H01L31/035254
摘要： A method of fabricating on optical detector, the method including providing a substrate that includes an optical waveguide formed therein and having a surface for fabricating microelectronic circuitry thereon; fabricating microelectronic circuitry on the substrate, the fabricating involving a plurality of sequential process phases; after a selected one of the plurality of sequential process phases has occurred and before the next process phase after the selected one of the plurality of process phases begins, fabricating an optical detector within the optical waveguide; and after fabricating the optical detector in the waveguide, completing the plurality of sequential process phases for fabricating the microelectronic circuitry.
摘要翻译：一种在光学检测器上制造的方法，所述方法包括提供包括其中形成的光波导并且具有用于在其上制造微电子电路的表面的衬底; 在衬底上制造微电子电路，该制造涉及多个连续的工艺阶段; 在所述多个顺序处理阶段中的所选择的一个已经发生并且在所述多个处理阶段中所选择的一个处理阶段开始之后的下一个处理阶段之前，在所述光波导内制造光学检测器; 并且在波导中制造光学检测器之后，完成用于制造微电子电路的多个顺序处理阶段。

8. 发明授权

US6103429A Technique for fabricating phase shift masks using self-aligned spacer formation 有权
标题翻译：使用自对准间隔物形成制造相移掩模的技术
公开(公告)号：US6103429A
公开(公告)日：2000-08-15
申请号：US161844
申请日：1998-09-28
申请人： Brian S. Doyle , Francisco A. Leon , Richard Elliot Schenker
发明人： Brian S. Doyle , Francisco A. Leon , Richard Elliot Schenker
IPC分类号： G03F1/00 , G03F1/28 , G03F1/30 , G03F9/00
CPC分类号： G03F1/28 , G03F1/30
摘要： A technique for fabricating a phase shift mask with multiple phase shifts by using self-aligned spacers to form phase shifting regions on a surface of a mask substrate. Three phase shifting regions are formed corresponding to 180.degree./120.degree./60.degree. phase shifts or delays on the surface of mask substrate. The three phase shifting regions are fabricated from three different dielectric materials, each having a different refractive indices. The first phase shifting region is formed by a photolithography technique, but the other two phase shifting regions are formed by the formation of self-aligned spacers. In an alternative technique, all three of the phase shifting regions are formed by the use of self-aligned spacers.
摘要翻译：一种通过使用自对准隔板来制造具有多个相移的相移掩模以在掩模基板的表面上形成相移区域的技术。形成对应于掩模基板表面上的180°/ 120°/ 60°相移或延迟的三个相移区域。三个相移区域由三种不同的介电材料制成，各自具有不同的折射率。通过光刻技术形成第一相移区域，但是通过形成自对准间隔物形成其它两个相移区域。在替代技术中，通过使用自对准间隔物形成所有三个相移区域。

9. 发明授权

US5586230A Surface sweeping method for surface movement in three dimensional topography simulation 失效
标题翻译：三维地形模拟中表面移动的表面扫描方法
公开(公告)号：US5586230A
公开(公告)日：1996-12-17
申请号：US148181
申请日：1993-11-05
申请人： Francisco A. Leon , Satoshi Tazawa
发明人： Francisco A. Leon , Satoshi Tazawa
IPC分类号： G06F17/50 , G06T17/10 , G06T17/00
CPC分类号： G06T17/10
摘要： A method for deforming a solid and avoiding the creation of self-intersecting solid structures in a topography simulator. In a topography simulated based on a solids modeling system, self-intersecting structures are solids which have boundaries that intersect. Such self-intersecting structures are invalid and cannot be processed. A general method for sweeping a solid surface to create a deformed solid and avoid the creation of self-intersecting solid structures is described, which include the steps of: providing a material solid with a surface represented as one or more segments; constructing a first segment solid for a first segment; performing a boolean set operation between the solid being swept and the first segment solid creating a temporary first solid; identifying a second segment; constructing a second segment solid for the second segment; and performing the boolean set operation between said temporary first solid and said first segment solid creating said deformed first solid. The case where simultaneous deposition and etch is occurring requires utilizes separate temporary deposition and etch solids for each segment both of which are swept to create the deformed solid.
摘要翻译：一种使固体变形并避免在地形模拟器中产生自相交固体结构的方法。在基于实体建模系统模拟的地形中，自相交结构是具有相交边界的固体。这种自相交结构无效，无法处理。描述了用于扫掠固体表面以产生变形固体并避免产生自相交固体结构的一般方法，其包括以下步骤：提供具有表示为一个或多个段的表面的材料固体; 为第一段构造第一段固体; 在被扫描的实体和创建临时的第一实体的第一段固定之间执行布尔组操作; 识别第二段; 为第二段构造第二段实体; 以及在所述临时第一实体和所述第一段固体之间执行布尔组合操作，创建所述变形的第一固体。同时沉积和蚀刻发生的情况需要对每个段进行单独的临时沉积和蚀刻固体，两个扫描都被扫过以产生变形的固体。

10. 发明申请

US20080290394A1 GATE ELECTRODE FOR A NONVOLATILE MEMORY CELL 有权
标题翻译：用于非易失性存储单元的门电极
公开(公告)号：US20080290394A1
公开(公告)日：2008-11-27
申请号：US12121591
申请日：2008-05-15
申请人： Xiangfeng DUAN , Jian Chen , J. Wallace Parce , Francisco A. Leon
发明人： Xiangfeng DUAN , Jian Chen , J. Wallace Parce , Francisco A. Leon
IPC分类号： H01L29/00 , H01L21/3205
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/42332 , H01L29/7883 , H01L29/7885
摘要： A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.
摘要翻译：非易失性存储单元包括在源极和漏极之间包括源极，漏极和沟道的衬底。隧道介电层覆盖在沟道上，并且局部电荷存储层设置在隧道介电层和控制电介质层之间。栅电极具有与控制电介质层相邻的第一表面，并且第一表面包括中部和两个边缘部分。根据一个实施例，中段限定一个平面，并且至少一个边缘部分远离平面延伸。优选地，远离平面延伸的边缘部分朝向栅电极的相对的第二表面会聚。根据另一实施例，非易失性存储单元的栅电极包括第一子层和第一子层上具有不同宽度的第二子层。

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