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1. 发明授权

US08716867B2 Forming interconnect structures using pre-ink-printed sheets 有权
标题翻译：使用预先印墨的薄片形成互连结构
公开(公告)号：US08716867B2
公开(公告)日：2014-05-06
申请号：US12778867
申请日：2010-05-12
申请人： Francis Ko , Chi-Chun Hsieh , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人： Francis Ko , Chi-Chun Hsieh , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号： B41F33/00
CPC分类号： H01L23/5384 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/49883 , H01L23/525 , H01L23/5328 , H01L24/05 , H01L24/13 , H01L24/14 , H01L2224/0401 , H01L2224/05572 , H01L2224/13009 , H01L2224/13147 , H01L2224/13644 , H01L2224/13655 , H01L2224/14181 , H01L2924/00014 , H01L2924/0002 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.
摘要翻译：形成器件的方法包括在电介质片上印刷导电图案以形成预先印墨的片材，以及将预印墨片材粘合到基片的一侧上。导电特征包括从衬底的第一主侧延伸到与第一主侧相对的衬底的第二主侧的贯通衬底。然后施加导电膏以将导电图案电耦合到衬底中的导电特征。

2. 发明申请

US20110277655A1 Forming Interconnect Structures Using Pre-Ink-Printed Sheets 有权
标题翻译：使用预墨水打印纸形成互连结构
公开(公告)号：US20110277655A1
公开(公告)日：2011-11-17
申请号：US12778867
申请日：2010-05-12
申请人： Francis Ko , Chi-Chun Hsieh , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人： Francis Ko , Chi-Chun Hsieh , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号： B41F33/00
CPC分类号： H01L23/5384 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/49883 , H01L23/525 , H01L23/5328 , H01L24/05 , H01L24/13 , H01L24/14 , H01L2224/0401 , H01L2224/05572 , H01L2224/13009 , H01L2224/13147 , H01L2224/13644 , H01L2224/13655 , H01L2224/14181 , H01L2924/00014 , H01L2924/0002 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.
摘要翻译：形成器件的方法包括在电介质片上印刷导电图案以形成预先印墨的片材，以及将预印墨片材粘合到基片的一侧上。导电特征包括从衬底的第一主侧延伸到与第一主侧相对的衬底的第二主侧的贯通衬底。然后施加导电膏以将导电图案电耦合到衬底中的导电特征。

3. 发明授权

US07767471B2 Auto routing for optimal uniformity control 有权
标题翻译：自动布线，实现最佳均匀度控制
公开(公告)号：US07767471B2
公开(公告)日：2010-08-03
申请号：US11830519
申请日：2007-07-30
申请人： Jean Wang , Francis Ko , Henry Lo , Chi-Chun Hsieh , Amy Wang , Chih-Wei Lai , Chun-Hsien Lin
发明人： Jean Wang , Francis Ko , Henry Lo , Chi-Chun Hsieh , Amy Wang , Chih-Wei Lai , Chun-Hsien Lin
IPC分类号： H01L21/00 , G01R31/26
CPC分类号： H01L22/12
摘要： A method for improving within-wafer uniformity is provided. The method includes forming an electrical component by a first process step and a second process step, wherein the electrical component has a target electrical parameter. The method includes providing a first plurality of production tools for performing the first process step; providing a second plurality of production tools for performing the second process step; providing a wafer; performing the first process step on the wafer using one of the first plurality of production tools; and selecting a first route including a first production tool from the second plurality of production tools. A within-wafer uniformity of the target electrical parameter on the wafer manufactured by the first route is greater than a second route including a second production tool in the second plurality of production tools.
摘要翻译：提供了一种提高晶片内均匀性的方法。该方法包括通过第一处理步骤和第二处理步骤形成电子部件，其中电气部件具有目标电参数。该方法包括提供用于执行第一处理步骤的第一多个生产工具; 提供用于执行所述第二处理步骤的第二多个生产工具; 提供晶片; 使用所述第一多个生产工具之一在所述晶片上执行所述第一工艺步骤; 以及从所述第二多个生产工具中选择包括第一生产工具的第一路线。由第一路径制造的晶片上的目标电参数的晶片内均匀性大于在第二多个生产工具中包括第二生产工具的第二路线。

4. 发明申请

US20090035883A1 Auto Routing for Optimal Uniformity Control 有权
标题翻译：自动路由优化均匀性控制
公开(公告)号：US20090035883A1
公开(公告)日：2009-02-05
申请号：US11830519
申请日：2007-07-30
申请人： Jean Wang , Francis Ko , Henry Lo , Chi-Chun Hsieh , Amy Wang , Chih-Wei Lai , Chun-Hsien Lin
发明人： Jean Wang , Francis Ko , Henry Lo , Chi-Chun Hsieh , Amy Wang , Chih-Wei Lai , Chun-Hsien Lin
IPC分类号： H01L21/66
CPC分类号： H01L22/12
摘要： A method for improving within-wafer uniformity is provided. The method includes forming an electrical component by a first process step and a second process step, wherein the electrical component has a target electrical parameter. The method includes providing a first plurality of production tools for performing the first process step; providing a second plurality of production tools for performing the second process step; providing a wafer; performing the first process step on the wafer using one of the first plurality of production tools; and selecting a first route including a first production tool from the second plurality of production tools. A within-wafer uniformity of the target electrical parameter on the wafer manufactured by the first route is greater than a second route including a second production tool in the second plurality of production tools.
摘要翻译：提供了一种提高晶片内均匀性的方法。该方法包括通过第一处理步骤和第二处理步骤形成电子部件，其中电气部件具有目标电参数。该方法包括：提供用于执行第一处理步骤的第一多个生产工具; 提供用于执行所述第二处理步骤的第二多个生产工具; 提供晶片; 使用所述第一多个生产工具之一在所述晶片上执行所述第一工艺步骤; 以及从所述第二多个生产工具中选择包括第一生产工具的第一路线。由第一路径制造的晶片上的目标电参数的晶片内均匀性大于在第二多个生产工具中包括第二生产工具的第二路线。

5. 发明授权

US07851234B2 System and method for enhanced control of copper trench sheet resistance uniformity 有权
标题翻译：增强铜沟片片电阻均匀性控制的系统和方法
公开(公告)号：US07851234B2
公开(公告)日：2010-12-14
申请号：US11947380
申请日：2007-11-29
申请人： Francis Ko , Jean Wang , Henry Lo , Chi-Chun Hsieh , Amy Wang
发明人： Francis Ko , Jean Wang , Henry Lo , Chi-Chun Hsieh , Amy Wang
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L22/14
摘要： A method is disclosed for controlling the sheet resistance of copper trenches formed on semiconductor wafers. The method includes forming a plurality of copper-filled trenches on a wafer, measuring the sheet resistance of each of the plurality of copper-filled trenches, and comparing the measured sheet resistance values to a predetermined sheet resistance value. Photolithography steps performed on subsequent wafers are adjusted according to a difference between the measured sheet resistance values and the predetermined value. In one embodiment, this adjustment takes the form of adjusting a photolithographic extension exposure energy to thereby adjust the cross-section of the resulting trenches.
摘要翻译：公开了一种用于控制形成在半导体晶片上的铜沟槽的薄层电阻的方法。该方法包括在晶片上形成多个铜填充沟槽，测量多个填充铜的沟槽中的每一个的薄层电阻，并将测得的薄层电阻值与预定薄层电阻值进行比较。根据测量的薄层电阻值和预定值之间的差异来调整在随后的晶片上执行的光刻步骤。在一个实施例中，该调整采取调整光刻延伸曝光能量的形式，从而调节所得到的沟槽的横截面。

6. 发明申请

US20090142860A1 SYSTEM AND METHOD FOR ENHANCED CONTROL OF COPPER TRENCH SHEET RESISTANCE UNIFORMITY 有权
标题翻译：增强铜镀层电阻均匀性的系统与方法
公开(公告)号：US20090142860A1
公开(公告)日：2009-06-04
申请号：US11947380
申请日：2007-11-29
申请人： Francis Ko , Jean Wang , Henry Lo , Chi-Chun Hsieh , Amy Wang
发明人： Francis Ko , Jean Wang , Henry Lo , Chi-Chun Hsieh , Amy Wang
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L22/14
摘要： A method is disclosed for controlling the sheet resistance of copper trenches formed on semiconductor wafers. The method includes forming a plurality of copper-filled trenches on a wafer, measuring the sheet resistance of each of the plurality of copper-filled trenches, and comparing the measured sheet resistance values to a predetermined sheet resistance value. Photolithography steps performed on subsequent wafers are adjusted according to a difference between the measured sheet resistance values and the predetermined value. In one embodiment, this adjustment takes the form of adjusting a photolithographic extension exposure energy to thereby adjust the cross-section of the resulting trenches.
摘要翻译：公开了一种用于控制形成在半导体晶片上的铜沟槽的薄层电阻的方法。该方法包括在晶片上形成多个铜填充沟槽，测量多个填充铜的沟槽中的每一个的薄层电阻，并将测得的薄层电阻值与预定薄层电阻值进行比较。根据测量的薄层电阻值和预定值之间的差异来调整在随后的晶片上执行的光刻步骤。在一个实施例中，该调整采取调整光刻延伸曝光能量的形式，从而调节所得到的沟槽的横截面。

7. 发明申请

US20080064127A1 METHOD AND SYSTEM FOR YIELD AND PRODUCTIVITY IMPROVEMENTS IN SEMICONDUCTOR PROCESSING 失效
标题翻译：半导体加工中的生产率和生产率改进方法与系统
公开(公告)号：US20080064127A1
公开(公告)日：2008-03-13
申请号：US11559781
申请日：2006-11-14
申请人： Chen-Hua Yu , Lawrance Sheu , Yi-Li Hsiao , Francis Ko
发明人： Chen-Hua Yu , Lawrance Sheu , Yi-Li Hsiao , Francis Ko
IPC分类号： H01L21/66
CPC分类号： H01L22/14 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor processing method includes processing a first substrate while detecting at least one first processing parameter value in a first apparatus. The first processing parameter is analyzed, thereby yielding at least one first predicted parameter value. The first predicted parameter value is compared with a first pre-defined parameter value, thereby yielding at least one first comparison result. A first recipe is applied corresponding to the first comparison result for processing a second substrate in the first apparatus.
摘要翻译：半导体处理方法包括在检测第一装置中的至少一个第一处理参数值的同时处理第一基板。分析第一处理参数，从而产生至少一个第一预测参数值。将第一预测参数值与第一预定义参数值进行比较，从而产生至少一个第一比较结果。对应于用于处理第一装置中的第二基板的第一比较结果应用第一配方。

8. 发明授权

US08682466B2 Automatic virtual metrology for semiconductor wafer result prediction 有权
标题翻译：自动虚拟测量用于半导体晶圆结果预测
公开(公告)号：US08682466B2
公开(公告)日：2014-03-25
申请号：US12025933
申请日：2008-02-05
申请人： Francis Ko , Chih-Wei Lai , Kewei Zuo , Henry Lo , Jean Wang , Ping-Hsu Chen , Chun-Hsien Lim , Chen-Hua Yu
发明人： Francis Ko , Chih-Wei Lai , Kewei Zuo , Henry Lo , Jean Wang , Ping-Hsu Chen , Chun-Hsien Lim , Chen-Hua Yu
IPC分类号： G06F17/50
CPC分类号： G05B23/0221
摘要： A method to enable wafer result prediction includes collecting manufacturing data from various semiconductor manufacturing tools and metrology tools; choosing key parameters using an autokey method based on the manufacturing data; building a virtual metrology based on the key parameters; and predicting wafer results using the virtual metrology.
摘要翻译：允许晶片结果预测的方法包括从各种半导体制造工具和计量工具收集制造数据; 使用基于制造数据的自动密钥方法选择关键参数; 基于关键参数构建虚拟计量; 并使用虚拟计量来预测晶圆结果。

9. 发明授权

US07642100B2 Method and system for yield and productivity improvements in semiconductor processing 失效
标题翻译：半导体加工中产量和生产率提高的方法和系统
公开(公告)号：US07642100B2
公开(公告)日：2010-01-05
申请号：US11559781
申请日：2006-11-14
申请人： Chen-Hua Yu , Lawrance Sheu , Yi-Li Hsiao , Francis Ko
发明人： Chen-Hua Yu , Lawrance Sheu , Yi-Li Hsiao , Francis Ko
IPC分类号： H01L21/66
CPC分类号： H01L22/14 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor processing method includes processing a first substrate while detecting at least one first processing parameter value in a first apparatus. The first processing parameter is analyzed, thereby yielding at least one first predicted parameter value. The first predicted parameter value is compared with a first pre-defined parameter value, thereby yielding at least one first comparison result. A first recipe is applied corresponding to the first comparison result for processing a second substrate in the first apparatus.
摘要翻译：半导体处理方法包括在检测第一装置中的至少一个第一处理参数值的同时处理第一基板。分析第一处理参数，从而产生至少一个第一预测参数值。将第一预测参数值与第一预定义参数值进行比较，从而产生至少一个第一比较结果。对应于用于处理第一装置中的第二基板的第一比较结果应用第一配方。

10. 发明授权

US08433434B2 Near non-adaptive virtual metrology and chamber control 有权
标题翻译：近非自适应虚拟计量和室控制
公开(公告)号：US08433434B2
公开(公告)日：2013-04-30
申请号：US12766626
申请日：2010-04-23
申请人： Amy Wang , Chen-Hua Yu , Jean Wang , Henry Lo , Francis Ko , Chih-Wei Lai , Kewei Zuo
发明人： Amy Wang , Chen-Hua Yu , Jean Wang , Henry Lo , Francis Ko , Chih-Wei Lai , Kewei Zuo
IPC分类号： G06F19/00
CPC分类号： G05B13/048
摘要： Embodiments of the present invention relate to a method for a near non-adaptive virtual metrology for wafer processing control. In accordance with an embodiment of the present invention, a method for processing control comprises diagnosing a chamber of a processing tool that processes a wafer to identify a key chamber parameter, and controlling the chamber based on the key chamber parameter if the key chamber parameter can be controlled, or compensating a prediction model by changing to a secondary prediction model if the key chamber parameter cannot be sufficiently controlled.
摘要翻译：本发明的实施例涉及一种用于晶片处理控制的近非自适应虚拟测量方法。根据本发明的实施例，一种用于处理控制的方法包括：诊断处理工具的室，其处理晶片以识别密钥室参数，以及如果密钥室参数可以基于密钥室参数来控制室如果密钥室参数不能被充分地控制，则通过改变为次级预测模型来控制或补偿预测模型。

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