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1. 发明授权

US06898076B2 Modular information processing system 有权
标题翻译：模块化信息处理系统
公开(公告)号：US06898076B2
公开(公告)日：2005-05-24
申请号：US10242296
申请日：2002-09-12
申请人： Francesco Pappalardo , Luigi Mantellassi
发明人： Francesco Pappalardo , Luigi Mantellassi
IPC分类号： G06F1/16
CPC分类号： G06F1/1632 , G06F1/1626
摘要： A modular information processing system is disclosed. The system includes an expansion device that embeds at least one internal peripheral without a controller and/or at least one port for connecting an external peripheral. The system further includes a hand-held computer that embeds control circuitry including at least one controller for the at least one internal peripheral or at least one external peripheral, and an interface for coupling the hand-held computer to the expansion device in a removable manner. In a mobile operating condition in which the hand-held computer is not coupled to the expansion device, the processing circuitry controls the hand-held computer. In an expanded operating condition in which the hand-held computer is coupled to the expansion device, the processing circuitry controls a personal computer formed by the hand-held computer and the expansion device. Also provided are a hand-held computer and an expansion device for use in modular information processing systems.
摘要翻译：公开了一种模块化信息处理系统。该系统包括在没有控制器的情况下嵌入至少一个内部外围设备的扩展设备和/或用于连接外部外围设备的至少一个端口。该系统还包括嵌入控制电路的手持计算机，该控制电路包括用于至少一个内部外围设备或至少一个外部外围设备的至少一个控制器，以及用于以可拆卸的方式将手持计算机连接到扩展装置的接口。在手持计算机没有耦合到扩展装置的移动操作条件下，处理电路控制手持计算机。在手持计算机耦合到扩展装置的扩展操作条件下，处理电路控制由手持计算机和扩展装置形成的个人计算机。还提供了一种用于模块化信息处理系统的手持计算机和扩展装置。

2. 发明授权

US07178044B2 Architecture for controlling dissipated power in a system-on-chip and related system 有权
标题翻译：在系统级芯片和相关系统中控制耗散功率的架构
公开(公告)号：US07178044B2
公开(公告)日：2007-02-13
申请号：US10440044
申请日：2003-05-16
申请人： Francesco Pappalardo , Luigi Mantellassi
发明人： Francesco Pappalardo , Luigi Mantellassi
IPC分类号： G06F1/26
CPC分类号： G06F9/30101 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3243 , G06F1/3287 , H01L23/34 , H01L2924/0002 , Y02D10/126 , Y02D10/128 , Y02D10/152 , Y02D10/171 , H01L2924/00
摘要： A system-on-chip (SoC) architecture includes a plurality of blocks, each including a power control module to selectively control the power dissipated by the bloc. For each block, a power register is provided to receive power control instructions to selectively control the respective power control module. The system also includes a power control unit for writing respective power control instructions into the power control registers of the blocks, whereby the power dissipated is controlled individually and independently for each block under the centralized control of the power control unit. For each block, a power status register is also provided to receive status information concerning power control within the respective block. The power control unit reads the status instructions from such power status registers.
摘要翻译：片上系统（SoC）架构包括多个块，每个块包括功率控制模块，用于选择性地控制由该块所耗散的功率。对于每个块，提供功率寄存器以接收功率控制指令以选择性地控制相应的功率控制模块。该系统还包括用于将各个功率控制指令写入块的功率控制寄存器的功率控制单元，由此在功率控制单元的集中控制下，对每个块单独且独立地控制功率消耗。对于每个块，还提供功率状态寄存器以接收关于相应块内的功率控制的状态信息。电源控制单元从这些电源状态寄存器读取状态指令。

3. 发明授权

US09378077B2 System for detecting operating errors in integrated circuits 有权
标题翻译：用于检测集成电路中的操作错误的系统
公开(公告)号：US09378077B2
公开(公告)日：2016-06-28
申请号：US12850056
申请日：2010-08-04
申请人： Francesco Pappalardo , Giuseppe Notarangelo , Elio Guidetti
发明人： Francesco Pappalardo , Giuseppe Notarangelo , Elio Guidetti
IPC分类号： G06F11/00 , G06F11/07 , G06F11/16 , H03K19/007
CPC分类号： G06F11/0751 , G06F11/1608 , G06F11/1629 , H03K19/007
摘要： Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse.
摘要翻译：通过以时钟信号计时的数字电子电路中的噪声脉冲引起的误差是通过在给定的时间间隔内为时钟信号提供至少一个额外的时钟信号偏移来检测的，并且对电路的至少一个分量执行比较两个版本之间的对应关系和相同的信号。比较由附加时钟信号计时，并且所述信号的两个版本之间不存在对应关系，通过噪声脉冲识别电路中感应的误差。

4. 发明授权

US07480354B2 Method and apparatus for channel estimation and cell search in cellular communication systems, and corresponding computer program product 有权
标题翻译：用于蜂窝通信系统中的信道估计和小区搜索的方法和装置，以及相应的计算机程序产品
公开(公告)号：US07480354B2
公开(公告)日：2009-01-20
申请号：US11051561
申请日：2005-02-04
申请人： Francesco Rimi , Alberto Serratore , Giuseppe Avellone , Francesco Pappalardo , Agostino Galluzzo
发明人： Francesco Rimi , Alberto Serratore , Giuseppe Avellone , Francesco Pappalardo , Agostino Galluzzo
IPC分类号： H03D1/00 , H04B7/216
CPC分类号： H04B1/7083 , H04B1/70735 , H04B2201/7071
摘要： In order to perform, according to a received signal (r), a channel-estimation procedure and a cell-search procedure in cellular communication systems, there are executed at least one first operation of correlation of said received signal (r) with secondary synchronization codes (SSC) and a second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS), whilst said channel-estimation procedure comprises a third operation of correlation of at least part of said received signal (r) with known midamble codes (mid, MPL, MPS), said first, second, and third correlation operation being executed by sending at least part (emidamble) of said received signal (r) to an input of a correlation bank. There are envisaged the operations of: sending, in a first time interval, the received signal (r) to said correlation bank for executing the first operation of correlation of said received signal (r) with secondary synchronization codes (SSC); sending, in a second time interval, at least part (emidamble) of said received signal (r) to said same correlation bank for executing the second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS); sending, in a second time interval, the received signal (r) to said same correlation bank for executing the third operation of correlation of at least part (emidamble) of said received signal (r) with known midamble codes (mid, MPL, MPS). Possible application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95 or WBCDMA.
摘要翻译：为了根据接收到的信号（r）执行蜂窝通信系统中的信道估计过程和小区搜索过程，执行所述接收信号（r）与辅助同步的相关的至少一个第一操作代码（SSC）和所述接收信号（r）与已知中间码（mid，MPL，MPS）的相关的第二操作，而所述信道估计过程包括所述接收信号的至少一部分所述第一，第二和第三相关运算是通过将所述接收信号（r）的至少一部分（emidamble）发送到相关库的输入来执行的。设想了以下操作：在第一时间间隔中将接收信号（r）发送到所述相关库，以执行所述接收信号（r）与辅同步码（SSC）的相关的第一操作; 在第二时间间隔中将所述接收信号（r）的至少一部分（emidamble）发送到所述相关相关库，以执行所述接收信号（r）与已知中间码（mid，MPL，MPS）的相关性的第二操作）; 将所接收的信号（r）在第二时间间隔中发送到所述相关相关库，以执行所述接收信号（r）的至少部分（emidamble）与已知中间码（mid，MPL，MPS）的相关的第三操作）。可能的应用是基于UMTS，CDMA2000，IS95或WBCDMA等标准的移动通信系统。

5. 发明申请

US20080016317A1 METHOD AND ARRANGEMENT FOR CACHE MEMORY MANAGEMENT, RELATED PROCESSOR ARCHITECTURE 有权
标题翻译：缓存记忆管理的方法与布置，相关处理器架构
公开(公告)号：US20080016317A1
公开(公告)日：2008-01-17
申请号：US11768462
申请日：2007-06-26
申请人： Francesco Pappalardo , Giuseppe Notarangelo , Elena Salurso , Elio Guidetti
发明人： Francesco Pappalardo , Giuseppe Notarangelo , Elena Salurso , Elio Guidetti
IPC分类号： G06F15/00
CPC分类号： G06F12/084 , G06F12/0886 , Y02D10/13
摘要： A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.
摘要翻译：耦合到包括处理器集群的处理器的数据高速缓冲存储器适于通过在数据高速缓冲存储器中提供用于存储用于处理的数据的数据位置同时操作标量和矢量数据。数据位置以标量模式或矢量模式进行访问。这通过明确地映射标量的数据位置和矢量的数据位置来完成。

6. 发明申请

US20050227725A1 Method and apparatus for channel estimation and cell search in cellular communication systems, and corresponding computer program product 有权
标题翻译：用于蜂窝通信系统中的信道估计和小区搜索的方法和装置，以及相应的计算机程序产品
公开(公告)号：US20050227725A1
公开(公告)日：2005-10-13
申请号：US11051561
申请日：2005-02-04
申请人： Francesco Rimi , Alberto Serratore , Giuseppe Avellone , Francesco Pappalardo , Agostino Galluzzo
发明人： Francesco Rimi , Alberto Serratore , Giuseppe Avellone , Francesco Pappalardo , Agostino Galluzzo
IPC分类号： H04B1/707 , H04B7/00
CPC分类号： H04B1/7083 , H04B1/70735 , H04B2201/7071
摘要： In order to perform, according to a received signal (r), a channel-estimation procedure and a cell-search procedure in cellular communication systems, there are executed at least one first operation of correlation of said received signal (r) with secondary synchronization codes (SSC) and a second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS), whilst said channel-estimation procedure comprises a third operation of correlation of at least part of said received signal (r) with known midamble codes (mid, MPL, MPS), said first, second, and third correlation operation being executed by sending at least part (emidamble) of said received signal (r) to an input of a correlation bank. There are envisaged the operations of: sending, in a first time interval, the received signal (r) to said correlation bank for executing the first operation of correlation of said received signal (r) with secondary synchronization codes (SSC); sending, in a second time interval, at least part (emidamble) of said received signal (r) to said same correlation bank for executing the second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS); sending, in a second time interval, the received signal (r) to said same correlation bank for executing the third operation of correlation of at least part (emidamble) of said received signal (r) with known midamble codes (mid, MPL, MPS). Possible application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95 or WBCDMA.
摘要翻译：为了根据接收到的信号（r）执行蜂窝通信系统中的信道估计过程和小区搜索过程，执行所述接收信号（r）与辅助同步的相关的至少一个第一操作代码（SSC）和所述接收信号（r）与已知中间码（mid，MPL，MPS）的相关的第二操作，而所述信道估计过程包括所述接收信号的至少一部分所述第一，第二和第三相关运算是通过将所述接收信号（r）的至少一部分（e midamble）发送到相关银行的输入。设想了以下操作：在第一时间间隔中将接收信号（r）发送到所述相关库，以执行所述接收信号（r）与辅同步码（SSC）的相关的第一操作; 在第二时间间隔中将所述接收信号（r）的至少一部分（e中间码）发送到所述相关相关库，以执行所述接收信号（r）与已知的中号码（中，MPL，MPS）; 在第二时间间隔中将接收到的信号（r）发送到所述相关相关库，以执行所述接收信号（r）的至少部分（e> mid amble amble amble amble）与已知的 midamble码（mid，MPL，MPS）。可能的应用是基于UMTS，CDMA2000，IS95或WBCDMA等标准的移动通信系统。

7. 发明授权

US08126084B2 Processing method for providing, starting from signals acquired by a set of sensors, an aggregate signal and data acquisition system using such method 有权
标题翻译：用于从由一组传感器获取的信号开始，使用这种方法提供聚合信号和数据采集系统的处理方法
公开(公告)号：US08126084B2
公开(公告)日：2012-02-28
申请号：US12844451
申请日：2010-07-27
申请人： Giuseppe Visalli , Francesco Pappalardo
发明人： Giuseppe Visalli , Francesco Pappalardo
IPC分类号： H04L27/00 , H03K9/00
CPC分类号： H04L12/2856
摘要： Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: acquiring said starting signals through respective sensors of a homogeneous sensors group; converting acquired signals in respective digital signals having data represented with a predetermined bits number; processing the digital signals to form aggregate signal. The processing step comprises the operations of: modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data; forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.
摘要翻译：用于从多个起始信号形成聚集信号的实施例，包括：通过均匀传感器组的相应传感器获取所述起始信号; 在具有以预定比特数表示的数据的各个数字信号中转换获取的信号; 处理数字信号以形成聚合信号。处理步骤包括以下操作：修改将每个这样的数字信号的数据格式从第一格式改变为第二格式的数字信号，第二格式中的每个数据是从第一格式的相应数据获得的，根据与所述数据相关联的置换方案和包括该数据的特定数字信号来排列比特位置; 形成通过对所述修改的数字信号相应数据作用的按位逻辑运算器获得所述聚合信号数据的聚合信号。

8. 发明授权

US07831804B2 Multidimensional processor architecture 有权
标题翻译：多维处理器架构
公开(公告)号：US07831804B2
公开(公告)日：2010-11-09
申请号：US12130861
申请日：2008-05-30
申请人： Francesco Pappalardo , Giuseppe Notarangelo , Elio Guidetti
发明人： Francesco Pappalardo , Giuseppe Notarangelo , Elio Guidetti
IPC分类号： G06F15/80
CPC分类号： G06F1/3203 , G06F1/3287 , G06F9/30036 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F15/8023 , Y02D10/171
摘要： A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which each include at least one microprocessor block having a computational part and a set of associated processing elements that are able to receive the same input signals. The number of associated processing elements is selectively variable in the direction of the column so as to exploit the parallelism of said signals. Additionally the processor architecture of the present invention enable dynamic switching between instruction parallelism and data parallel processing typical of vectorial functionality. The architecture can be scaled in various dimensions in an optimal configuration for the algorithm to be executed.
摘要翻译：处理器架构包括用于处理输入信号的多个处理元件。该架构根据包括行和列的矩阵来组织，其列包括至少一个具有计算部分的微处理器块和能够接收相同输入信号的一组相关联的处理元件。相关联的处理元件的数量在列的方向上选择性地变化，以便利用所述信号的并行性。另外，本发明的处理器体系结构能够实现指令并行性与典型的矢量功能的数据并行处理之间的动态切换。该架构可以在要执行的算法的最佳配置中以各种尺寸缩放。

9. 发明授权

US07398289B2 Method and device for floating-point multiplication, and corresponding computer-program product 有权
标题翻译：浮点乘法的方法和装置，以及相应的计算机程序产品
公开(公告)号：US07398289B2
公开(公告)日：2008-07-08
申请号：US10887225
申请日：2004-07-08
申请人： Giuseppe Visalli , Francesco Pappalardo
发明人： Giuseppe Visalli , Francesco Pappalardo
IPC分类号： G06F7/487
CPC分类号： G06F7/4876 , G06F7/483 , G06F7/49936 , G06F7/49947
摘要： In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to the mantissa. In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa to a value 1, in order to obtain a mantissa having a value comprised between 0.5 and 1. Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point teal numbers according to the IEEE754 standard. Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.
摘要翻译：在用于以符号，指数和尾数二进制方式编码的浮点实数的乘法的方法中，尾数的乘法设想了部分乘积的计算步骤，该部分乘积由对应于尾数的一组附加物构成。为了减小设计用于计算的电路的尺寸和功率消耗，采用二进制编码方法，其设想将尾数的第一位设置为值1，以便获得包含在0.5之间的值的尾数还提出了用于实现乘法的产品和电路的舍入的方法。还示出了根据IEEE754标准从浮点实数转换和编码的电路。优先应用于便携式和/或无线电子设备，例如移动电话和PDA，具有低功耗要求。

10. 发明授权

US07397944B2 Processing pipeline of pixel data of a color image acquired by a digital sensor 有权
标题翻译：处理由数字传感器获取的彩色图像的像素数据的流水线
公开(公告)号：US07397944B2
公开(公告)日：2008-07-08
申请号：US11119223
申请日：2005-04-29
申请人： Giuseppe Spampinato , Francesco Pappalardo , Paolo Antonino Foderá , Francesco Virlinzi , Alessandro Capra
发明人： Giuseppe Spampinato , Francesco Pappalardo , Paolo Antonino Foderá , Francesco Virlinzi , Alessandro Capra
IPC分类号： G06K9/00 , G06K9/36 , G06F3/038 , H04N9/04
CPC分类号： G06T3/4015 , G06T1/20
摘要： A color image processing pipeline performs an interpolation on color data to generate triplets located at distinct pixel locations. The pipeline includes defect correction and image enhancement blocks having a first color interpolation block for generating RGB information for each pixel of an input image pixel pattern, and a second color interpolation block for receiving the RGB information to provide enhanced RGB pattern pixels. Dedicated line memories and delay circuits associated with the defect correction and image enhancement blocks permit real-time processing of pixel data. First and second read/write buffers store a subset or pixel block of the image data, and invert a scanning mode of pixel data being fed to the dedicated line memories and delay circuits associated to at least the first color interpolation block, from row-wise to column-wise, for each subset of data to be stored therein.
摘要翻译：彩色图像处理流水线对颜色数据执行内插以产生位于不同像素位置处的三元组。该管线包括缺陷校正和图像增强块，其具有用于产生输入图像像素图案的每个像素的RGB信息的第一颜色内插块和用于接收RGB信息以提供增强的RGB图案像素的第二颜色内插块。与缺陷校正和图像增强块相关联的专用行存储器和延迟电路允许像素数据的实时处理。第一和第二读/写缓冲器存储图像数据的子集或像素块，并反转正被馈送到专用行存储器的像素数据的扫描模式和与至少第一颜色内插块相关联的延迟电路，对于要存储在其中的数据的每个子集，按列逐列。

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