专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2010091447A Device and method for measuring surface shape 有权
标题翻译：用于测量表面形状的装置和方法
公开(公告)号：JP2010091447A
公开(公告)日：2010-04-22
申请号：JP2008262469
申请日：2008-10-09
申请人： Foundation For Advancement Of International Science , Tohoku Univ , 国立大学法人東北大学 , 財団法人国際科学振興財団
发明人： OMI TADAHIRO , TERAMOTO AKINOBU , YODA MASAHIRO
IPC分类号： G01Q30/12 , G01B21/30 , G01Q60/24
摘要： PROBLEM TO BE SOLVED: To provide a device and method for stably measuring the surface shape while eliminating the effect of static charge and without causing a change in the surface of an active object to be measured in measuring the surface shape using a scanning type probe microscope. SOLUTION: The scanning type probe microscope 100 has a measurement probe 104a for scanning the surface of a sample 101 to be measured, and a solution 102 is provided between the sample 101 to be measured and the measurement probe 104a over at least the measurement range of the sample 101 to be measured. The solution 102 is used for preventing the surface of the sample 101 to be measured and the measurement probe 104a from being charged and preventing a natural oxide film or organic material from growing or being adsorbed by the surface of the sample 101 to be measured. As the solution, for example, isopropyl alcohol (IPA) is cited, but a gas having the physical properties satisfying the above requirements may be used instead of the solution. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在消除静电荷的效果的同时稳定地测量表面形状并且在使用扫描测量表面形状时不引起要测量的活动物体的表面的变化的装置和方法型探针显微镜。解决方案：扫描型探针显微镜100具有用于扫描要测量的样品101的表面的测量探针104a，并且在被测量样品101和测量探针104a之间至少设置有溶液102 要测量的样品101的测量范围。溶液102用于防止样品101的表面被测量，并且测量探针104a被充电并且防止天然氧化物膜或有机材料生长或被被测量的样品101的表面吸附。作为溶液，例如可举出异丙醇（IPA），但也可以使用具有满足上述要求的物性的气体来代替溶液。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2008251666A Three-dimensional structure semiconductor device 审中-公开
标题翻译：三维结构半导体器件
公开(公告)号：JP2008251666A
公开(公告)日：2008-10-16
申请号：JP2007088444
申请日：2007-03-29
申请人： Foundation For Advancement Of International Science , Tohoku Univ , 国立大学法人東北大学 , 財団法人国際科学振興財団
发明人： OMI TADAHIRO , YODA MASAHIRO
IPC分类号： H01L25/065 , H01L21/8234 , H01L23/52 , H01L25/07 , H01L25/18 , H01L27/00 , H01L27/088
CPC分类号： H01L27/0688 , H01L21/8221 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a three-dimensional structure semiconductor device which prevents an increase in the area of a chip and increases the operation frequency of the chip.
SOLUTION: The three-dimensional structure semiconductor device comprises a first integrated circuit including a plurality of regions formed in a first semiconductor layer and a first wiring layer formed on the first semiconductor layer, a first insulating layer overlaid on the first wiring layer, and a second integrated circuit including a plurality of regions formed in a second semiconductor layer overlaid on the first insulating layer and a second wiring layer formed on the second semiconductor layer. The first integrated circuit is connected electrically to the second integrated circuit through an interconnect penetrating the integrated circuits in the direction of lamination of the layers. At least one of two-way data communication, control signal supply, and clock signal supply between the first and second integrated circuits is carried out through the penetrating interconnect.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种三维结构半导体器件，其防止芯片的面积增加并增加芯片的工作频率。解决方案：三维结构半导体器件包括第一集成电路，其包括形成在第一半导体层中的多个区域和形成在第一半导体层上的第一布线层，第一绝缘层覆盖在第一布线层以及第二集成电路，包括形成在覆盖在第一绝缘层上的第二半导体层中的多个区域和形成在第二半导体层上的第二布线层。第一集成电路通过在层的层叠方向穿过集成电路的互连件与第二集成电路电连接。第一和第二集成电路之间的双向数据通信，控制信号供给和时钟信号供给中的至少一个通过穿透互连来进行。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2013062514A Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：JP2013062514A
公开(公告)日：2013-04-04
申请号：JP2012227740
申请日：2012-10-15
申请人： Tohoku Univ , 国立大学法人東北大学 , Foundation For Advancement Of International Science , 公益財団法人国際科学振興財団
发明人： OMI TADAHIRO , TERAMOTO AKINOBU , KURODA MICHIHITO
IPC分类号： H01L21/336 , H01L21/28 , H01L21/304 , H01L21/316 , H01L21/318 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L29/417 , H01L29/78 , H01L29/786
CPC分类号： H01L29/045 , H01L21/02057 , H01L21/28194 , H01L21/28202 , H01L21/823807 , H01L21/823835 , H01L21/82385 , H01L21/84 , H01L27/1203 , H01L29/41766 , H01L29/456 , H01L29/518 , H01L29/785 , H01L2029/7857
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing method which can increase a drain current obtained correspondingly to a certain amount of drain voltage and gate voltage.SOLUTION: A manufacturing method of a semiconductor device including a channel region, a source region and a drain region, a total of two first electrodes electrically connected to the source region and the drain region, respectively, and a second electrode provided on the channel region via a gate insulation film, comprises: cleaning a surface of the gate insulation film by using a cleaning solvent in which IPA is added to hydrogenated ultra pure water containing oxygen of not more than 1 ppb, in a nitrogen atmosphere containing oxygen of not more than 1ppb and in a state of being light shielded; and performing formation by isotropic oxidation or nitriding to make flatness of an interface between the channel region and the gate insulation film become a peak-to-valley value of not more than 0.3 nm in 2 nm length in a direction from the source region toward the drain region, and make a resistance from the first electrode to the channel region be not more than 4 Ω μm.
摘要翻译：要解决的问题：提供一种可以增加相应于一定量的漏极电压和栅极电压而获得的漏极电流的半导体制造方法。解决方案：一种包括沟道区，源区和漏区的半导体器件的制造方法，分别与源区和漏区电连接的总共两个第一电极和设置在源极区和漏极区上的第二电极通过栅极绝缘膜的沟道区域包括：通过使用将IPA添加到含氧量不超过1ppb的氢的超纯水中的清洗溶剂，在含有氧的氮气氛中，清洁栅极绝缘膜的表面不超过1ppb，处于遮光状态; 并且通过各向同性氧化或氮化进行形成，使得沟道区域和栅极绝缘膜之间的界面的平坦度在从源极区域朝向源极区域的方向上成为2nm长度的不大于0.3nm的峰谷值漏极区域，并且从第一电极到沟道区域的电阻不大于4Ωμm。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2010287897A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010287897A
公开(公告)日：2010-12-24
申请号：JP2010156621
申请日：2010-07-09
申请人： Foundation For Advancement Of International Science , Tohoku Univ , 国立大学法人東北大学 , 財団法人国際科学振興財団
发明人： OMI TADAHIRO , TERAMOTO AKINOBU , KURODA MICHIHITO
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/08 , H01L27/092 , H01L29/417 , H01L29/786
CPC分类号： H01L29/045 , H01L21/02057 , H01L21/28194 , H01L21/28202 , H01L21/823807 , H01L21/823835 , H01L21/82385 , H01L21/84 , H01L27/1203 , H01L29/41766 , H01L29/456 , H01L29/518 , H01L29/785 , H01L2029/7857
摘要： PROBLEM TO BE SOLVED: To provide a high-speed semiconductor device operable at a clock frequency ≥around 10 GHz. SOLUTION: This semiconductor device includes n-MOSFETs 100n and a p-MOSFET 100p; a surface of a first region for forming a channel of the n-MOSFET has a surface within ±10° from a (100) surface or a surface within ±10° from a (110) surface; a surface of a second region for forming a channel of the p-MOSFET has a surface within ±10° from a (110) surface or a surface within ±10° from a (100) surface; resistance from each of the first and second regions to each of a source electrode and a drain electrode at both ends is set ≤4 Ω μcm; an interface between the first region and a first gate insulating layer and an interface between the second region and a second gate insulating layer are set at flatness in which a peak-to-valley value at a length of 2 nm in a direction from a source of each region toward a drain is ≤0.3 nm. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供可在10GHz以上的时钟频率工作的高速半导体器件。解决方案：该半导体器件包括n-MOSFET 100n和p-MOSFET 100p; 用于形成n-MOSFET的沟道的第一区域的表面具有与（100）表面±10°的表面或距（110）表面±10°以内的表面; 用于形成p-MOSFET的沟道的第二区域的表面具有与（110）表面在±10°内的表面或距离（100）表面±10°内的表面; 从第一和第二区域的每一个到两端的源电极和漏电极的电阻设定为≤4Ωμcm; 在第一区域和第一栅极绝缘层之间的界面以及第二区域和第二栅极绝缘层之间的界面被设置为平坦度，其中在距离源极的方向上具有2nm的长度的峰谷值的每个区域朝向漏极≤3.3nm。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2010109143A Method of forming contact, method of manufacturing semiconductor device, and semiconductor device 有权
标题翻译：形成接触方法，制造半导体器件的方法和半导体器件
公开(公告)号：JP2010109143A
公开(公告)日：2010-05-13
申请号：JP2008279536
申请日：2008-10-30
申请人： Foundation For Advancement Of International Science , Tohoku Univ , 国立大学法人東北大学 , 財団法人国際科学振興財団
发明人： OMI TADAHIRO , TERAMOTO AKINOBU , ISOGAI TATSUNORI , TANAKA HIROAKI
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/8238 , H01L23/52 , H01L27/092 , H01L29/78 , H01L29/786
CPC分类号： H01L21/823814 , H01L21/28079 , H01L21/28518 , H01L21/823835 , H01L27/092 , H01L29/41733 , H01L29/458 , H01L29/4958 , H01L29/66772 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, wherein low-resistivity contacts are achieved. SOLUTION: In a state where a first metal layer coming into contact with a semiconductor is covered with an anti-oxidation second metal layer, only the first metal layer is silicided to form a silicide layer where oxygen is not mixed. A metal of which the difference in work function from the semiconductor is a prescribed value is used as a material of the first metal layer, and a metal which doesn't react with the first metal layer at an annealing temperature is used as a material of the second metal layer. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，其中实现了低电阻接触。解决方案：在与半导体接触的第一金属层被抗氧化第二金属层覆盖的状态下，仅第一金属层被硅化以形成不混合氧的硅化物层。作为第一金属层的材料，使用与半导体的功能差异为规定值的金属，在退火温度下不与第一金属层反应的金属作为第二金属层。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2009277994A Contact forming method, method for manufacturing for semiconductor device, and semiconductor device 审中-公开
标题翻译：接触形成方法，用于制造半导体器件的方法和半导体器件
公开(公告)号：JP2009277994A
公开(公告)日：2009-11-26
申请号：JP2008129692
申请日：2008-05-16
申请人： Foundation For Advancement Of International Science , Tohoku Univ , 国立大学法人東北大学 , 財団法人国際科学振興財団
发明人： OMI TADAHIRO , TERAMOTO AKINOBU , TANAKA HIROAKI , ISOGAI TATSUNORI
IPC分类号： H01L21/336 , H01L21/265 , H01L21/28 , H01L29/417 , H01L29/78
CPC分类号： H01L21/28518 , H01L21/26513 , H01L21/28052 , H01L21/324 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/66575
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing for a semiconductor device that realizes a contact having low resistivity.
SOLUTION: The method for manufacturing includes a step of implanting a p-type or n-type impurity ion into a silicon portion of the semiconductor device that is to be made into an p-type or n-type silicon region, a step of forming a contact metal film on the surface of the contact region, following the ion implantation step, without carrying out heat treatment for activating the implanted ion, and a step of reacting the metal with the silicon portion by heating to form a silicide of the metal. It is preferable that the method include a step of activating the implanted ion by heat treatment that follows the formation of the metal film.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供实现具有低电阻率的接触的半导体器件的制造方法。解决方案：制造方法包括将p型或n型杂质离子注入到要制成p型或n型硅区的半导体器件的硅部分中的步骤，在离子注入步骤之后，在接触区域的表面上形成接触金属膜的步骤，而不进行用于激活注入离子的热处理，以及通过加热使金属与硅部分反应以形成硅化物的步骤金属。优选的是，该方法包括通过在形成金属膜之后进行热处理来激活注入离子的步骤。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2013012768A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013012768A
公开(公告)日：2013-01-17
申请号：JP2012194693
申请日：2012-09-05
申请人： Tohoku Univ , 国立大学法人東北大学 , Foundation For Advancement Of International Science , 公益財団法人国際科学振興財団
发明人： OMI TADAHIRO , TERAMOTO AKINOBU , KURODA MICHIHITO
IPC分类号： H01L29/786 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To solve such a problem that, in an inversion-type transistor, an intrinsic-type transistor and an accumulation-type transistor of an accumulation layer current controlled type of a semiconductor layer, variation in threshold voltage is increased in a miniature generation by statistical variation in an impurity atom concentration, therefor making it hard to keep the reliability of an LSI.SOLUTION: A bulk-current controlled accumulation type transistor is obtained, the transistor being formed by controlling the film thickness and the impurity atomic concentration of a semiconductor layer so that the thickness of a depletion layer becomes larger than the film thickness of the semiconductor layer. By making the film thickness of the semiconductor layer to be 100 nm and the impurity concentration to be higher than 2×10[cm], for example, the standard deviation of variation in threshold value can be made smaller than variation in power source voltage.
摘要翻译：解决的问题为了解决这样一个问题，在反型型晶体管中，本征型晶体管和累积层电流控制型半导体层的累积型晶体管，阈值电压的变化是通过杂质原子浓度的统计学变化在微型产生中增加，从而难以保持LSI的可靠性。解决方案：通过控制半导体层的膜厚度和杂质原子浓度形成晶体管，从而使耗尽层的厚度大于薄膜厚度半导体层。通过使半导体层的膜厚为100nm，杂质浓度高于2×10 =“POST”> 3 < / SP>]，例如，可以使阈值的变化的标准偏差小于电源电压的变化。版权所有（C）2013，JPO＆INPIT

8. 发明专利

JP2009267195A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009267195A
公开(公告)日：2009-11-12
申请号：JP2008116701
申请日：2008-04-28
申请人： Foundation For Advancement Of International Science , Tohoku Univ , 国立大学法人東北大学 , 財団法人国際科学振興財団
发明人： OMI TADAHIRO , TERAMOTO AKINOBU , KURODA MICHIHITO
IPC分类号： H01L29/786 , H01L21/8238 , H01L27/08 , H01L27/092
CPC分类号： H01L27/1203 , H01L27/0883 , H01L27/092 , H01L29/045 , H01L29/458 , H01L29/78654 , H01L29/78696
摘要： PROBLEM TO BE SOLVED: To solve the problem that the reliability of an LSI is hardly maintained because the variation in threshold voltage becomes large in a microfabrication generation due to statistical variation in concentration in impurity atoms in an Inversion-type transistor, an Intrinsic-type transistor and a storage layer current control Accumulation-type transistor of a semiconductor layer.
SOLUTION: A bulk current control Accumulation-type transistor can be obtained by controlling the film thickness of the semiconductor layer and the concentration in impurity atoms so that the thickness of a depletion layer may be larger than the film thickness of the semiconductor layer. For example, the film thickness of the semiconductor layer is set to 100 nm and the impurity concentration is set higher than 2×10
17 [cm
-3 ], thereby making the standard deviation of variation in threshold voltage smaller than the variation in power supply voltage.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题为了解决由于反相型晶体管中的杂质原子的浓度的统计学变化而导致的微细加工生成中阈值电压的变化变大而难以维持LSI的可靠性的问题，本征型晶体管和存储层电流控制半导体层的累积型晶体管。解决方案：可以通过控制半导体层的膜厚度和杂质原子的浓度来获得体电流控制累积型晶体管，使得耗尽层的厚度可以大于半导体层的膜厚度。例如，将半导体层的膜厚设定为100nm，将杂质浓度设定为高于2×10 [cm 3〜SP 3]，从而使阈值电压变化的标准偏差小于电源电压的变化。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2009266967A Ferroelectric film, semiconductor device having ferroelectric film, and method of manufacturing the same 审中-公开
标题翻译：电磁膜，具有电磁膜的半导体器件及其制造方法
公开(公告)号：JP2009266967A
公开(公告)日：2009-11-12
申请号：JP2008112994
申请日：2008-04-23
申请人： Foundation For Advancement Of International Science , Tohoku Univ , 国立大学法人東北大学 , 財団法人国際科学振興財団
发明人： OMI TADAHIRO , TAKAHASHI ICHIRO
IPC分类号： H01L21/8246 , C23C14/08 , C23C14/58 , H01L21/316 , H01L27/105
CPC分类号： H01L21/28291 , C23C14/024 , C23C14/08 , C23C14/5826 , H01G7/06 , H01J37/32192 , H01J37/32724 , H01J2237/2001 , H01L21/31691 , H01L28/55 , H01L29/78391
摘要： PROBLEM TO BE SOLVED: To provide a ferroelectric film enabling more miniaturization and more stable operation than the film in the prior art, and having excellent adhesiveness with a base, to provide a semiconductor device using the ferroelectric film and a method of manufacturing the semiconductor device, and to provide a ferroelectric device using the ferroelectric film.
SOLUTION: The semiconductor device 71 has a substrate 55, an insulator 56, an yttrium oxide film 66, a ferroelectric film (STN film) 57 and an upper electrode 62. The yttrium oxide film 66 is used as a base in crystallizing the ferroelectric film (STN film) 57. The yttrium oxide film 66 contains oxygen, and its lattice information is approximate to the crystal of the ferroelectric film (STN film) 57. Accordingly, when the STN is crystallized on the yttrium oxide film 66, the ferroelectric film (STN film) 57 having no oxygen loss and ≥200 kV/cm anti-electric field can be obtained.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种铁电膜，其能够比现有技术中的膜更加小型化和更稳定的操作，并且与基底具有优异的粘合性，以提供使用该铁电体膜的半导体器件和制造方法并且提供使用铁电体膜的铁电体元件。解决方案：半导体器件71具有衬底55，绝缘体56，氧化钇膜66，铁电体膜（STN膜）57和上电极62.氧化钇膜66用作结晶中的碱铁电体膜（STN膜）57。氧化钇膜66含有氧，其晶格信息接近铁电体膜（STN膜）57的晶体。因此，当STN在氧化钇膜66上结晶时，可以获得没有氧损失的强电介质膜（STN膜）57和≥200kV/ cm的抗电场。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2008147365A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008147365A
公开(公告)日：2008-06-26
申请号：JP2006332003
申请日：2006-12-08
申请人： Foundation For Advancement Of International Science , Tohoku Univ , 国立大学法人東北大学 , 財団法人国際科学振興財団
发明人： OMI TADAHIRO , TERAMOTO AKINOBU , TANAKA KOTARO
IPC分类号： H01L29/12 , H01L21/318 , H01L21/336 , H01L29/78
CPC分类号： H01L21/049 , H01J37/32192 , H01L29/1608 , H01L29/518 , H01L29/6606 , H01L29/66068 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To solve the problem that a gate oxide film having good electrical characteristics can not be obtained when a gate insulating film is formed on an SiC substrate according to a usual silicon oxide film forming technology.
SOLUTION: A film having smaller hysteresis and a higher breakdown voltage can be obtained by decreasing the carbon content in the gate insulating film on the SiC substrate. Accordingly, after a silicon oxide film is formed on the SiC substrate using a plasma processing apparatus, the gate insulating film having excellent electrical characteristics can be obtained by exposing the formed silicon oxide film to radicals each containing a nitrogen atom to reform it.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题为了解决在通常的氧化硅膜形成技术中在SiC衬底上形成栅极绝缘膜时不能获得具有良好电特性的栅极氧化膜的问题。解决方案：通过降低SiC衬底上的栅极绝缘膜中的碳含量，可以获得具有较小磁滞和较高击穿电压的膜。因此，在使用等离子体处理装置在SiC衬底上形成氧化硅膜之后，可以通过将形成的氧化硅膜暴露于含有氮原子的基团进行改性来获得具有优异的电特性的栅极绝缘膜。版权所有（C）2008，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式