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1. 发明申请

US20060077275A1 Processor-controlled timing generator for multiple image sensors 有权
公开(公告)号：US20060077275A1
公开(公告)日：2006-04-13
申请号：US10963494
申请日：2004-10-11
申请人： Feng Pan , Yasu Noguchi , Young Kim
发明人： Feng Pan , Yasu Noguchi , Young Kim
IPC分类号： H04N5/335
CPC分类号： H04N5/335
摘要： A versatile analog front end and timing generator (AFE/TG) integrated circuit is capable of supplying horizontal and vertical timing signals to a large number of disparate image sensors. In a first novel aspect, the AFE/TG includes an output mode wherein multiple identical AFE/TGs output digitized sensor data to a single digital image processor (DIP) without intervening multiplexing circuitry. In a second novel aspect, the AFE/TG includes a processor that executes a program. Execution of the program controls the detailed timing of horizontal and vertical timing signals output from the AFE/TG. At boot time, the program is loaded into the AFE/TG via a serial bus. In a third novel aspect, the processor is clocked by a clock signal with a relatively long clock period. A DLL and associated set/reset circuitry allows the processor to generate and control timing signals with a resolution substantially greater than clock period of the processor.

2. 发明授权

US07557849B2 Processor-controlled timing generator for multiple image sensors 有权
标题翻译：用于多个图像传感器的处理器控制定时发生器
公开(公告)号：US07557849B2
公开(公告)日：2009-07-07
申请号：US10963494
申请日：2004-10-11
申请人： Feng F. Pan , Yasu Noguchi , Young Kim
发明人： Feng F. Pan , Yasu Noguchi , Young Kim
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H04N5/335
摘要： A versatile analog front end and timing generator (AFE/TG) integrated circuit is capable of supplying horizontal and vertical timing signals to a large number of disparate image sensors. In a first novel aspect, the AFE/TG includes an output mode wherein multiple identical AFE/TGs output digitized sensor data to a single digital image processor (DIP) without intervening multiplexing circuitry. In a second novel aspect, the AFE/TG includes a processor that executes a program. Execution of the program controls the detailed timing of horizontal and vertical timing signals output from the AFE/TG. At boot time, the program is loaded into the AFE/TG via a serial bus. In a third novel aspect, the processor is clocked by a clock signal with a relatively long clock period. A DLL and associated set/reset circuitry allows the processor to generate and control timing signals with a resolution substantially greater than clock period of the processor.
摘要翻译：通用的模拟前端和定时发生器（AFE / TG）集成电路能够向大量不同的图像传感器提供水平和垂直定时信号。在第一个新颖的方面，AFE / TG包括输出模式，其中多个相同的AFE / TG将数字化的传感器数据输出到单个数字图像处理器（DIP），而不需要插入多路复用电路。在第二个新颖的方面，AFE / TG包括执行程序的处理器。程序的执行控制从AFE / TG输出的水平和垂直定时信号的详细时序。在引导时，程序通过串行总线加载到AFE / TG中。在第三个新颖的方面，处理器由具有较长时钟周期的时钟信号计时。 DLL和相关联的设置/复位电路允许处理器以比处理器的时钟周期大得多的分辨率产生和控制定时信号。

3. 发明授权

US07787026B1 Continuous burst mode digital camera 有权
标题翻译：连拍模式数码相机
公开(公告)号：US07787026B1
公开(公告)日：2010-08-31
申请号：US10981213
申请日：2004-11-04
申请人： Kevin Flory , Hung Do , William Stemper , Yasu Noguchi , Steven D. Loi
发明人： Kevin Flory , Hung Do , William Stemper , Yasu Noguchi , Steven D. Loi
IPC分类号： H04N5/76 , H04N3/14 , H04N9/083 , G06K9/32
CPC分类号： H04N5/232 , H04N1/2166 , H04N5/23245 , H04N5/2628 , H04N5/772 , H04N5/907 , H04N9/045 , H04N9/07 , H04N9/735 , H04N9/8042 , H04N2101/00 , H04N2201/3247
摘要： A camera has a continuous full-resolution burst mode wherein a sequence of full-resolution images is captured, is image processed by a pipeline of dedicated hardware image processing engines, is zoomed by a zoom engine, is compressed by a compression engine, and is stored into nonvolatile storage as a sequence of discrete files. The capturing of images and the storing of files continues at a rate of at least three frames per second until the user indicates burst mode operation is to stop or until nonvolatile storage becomes filled. Although the camera has a buffer memory into which raw sensor data is placed before image processing, the number of images that can be captured in a single burst is not limited by the size of the buffer memory. The cost of a consumer market camera having continuous burst mode capability is therefore reduced by reducing the required amount of buffer memory.
摘要翻译：相机具有连续的全分辨率突发模式，其中捕获全序列的全分辨率图像，由缩放引擎缩放的专用硬件图像处理引擎的流水线进行图像处理，由压缩引擎压缩，并且是作为一系列离散文件存储到非易失性存储器中。图像的捕获和文件的存储以至少三帧/秒的速率继续，直到用户指示突发模式操作停止或直到非易失性存储器被填满。虽然相机具有在图像处理之前放置原始传感器数据的缓冲存储器，但是可以在单个突发中捕获的图像的数量不受缓冲存储器的大小的限制。因此，通过减少所需量的缓冲存储器来降低具有连续突发模式能力的消费者市场相机的成本。

4. 发明申请

US20060077276A1 Analog front end timing generator (AFE/TG) having a bit slice output mode 有权
标题翻译：具有位片输出模式的模拟前端定时发生器（AFE / TG）
公开(公告)号：US20060077276A1
公开(公告)日：2006-04-13
申请号：US11044379
申请日：2005-01-27
申请人： Yasu Noguchi
发明人： Yasu Noguchi
IPC分类号： H04N5/335
CPC分类号： H04N5/335
摘要： A versatile analog front end and timing generator (AFE/TG) integrated circuit has output modes wherein multiple identical AFE/TGs output digitized sensor data to a single digital image processor (DIP) without intervening discrete multiplexing circuitry. In one embodiment, the AFE/TG is operable in either a bit slice mode or a time slice mode. In the bit slice mode, each of the multiple AFE/TGs sections up a word of pixel information into subsets of bits, and then communicates the subsets in parallel, one subset after another, across point-to-point connections to corresponding terminals of the DIP. The DIP captures the subsets of bits, and reassembles the subsets to recreate the word of pixel information. Each of the multiple AFE/TGs communicates words of pixel information to a different set of terminals on the DIP in this way, thereby avoiding timing complications, loading and/or expense associated with communicating the pixel information using time multiplexing techniques.
摘要翻译：多功能模拟前端和定时发生器（AFE / TG）集成电路具有输出模式，其中多个相同的AFE / TG将数字化传感器数据输出到单个数字图像处理器（DIP），而无需插入离散复用电路。在一个实施例中，AFE / TG可以在位片模式或时间片模式中操作。在位片模式中，多个AFE / TG中的每一个将像素信息的字段分成比特的子集，然后并行地将子集彼此一个子集，通过点对点连接传送到相应的终端蘸。 DIP捕获位的子集，并重新组合子集以重新创建像素信息的单词。多个AFE / TG中的每一个以这种方式将像素信息的字传送到DIP上的不同终端集合，从而避免与使用时间复用技术传送像素信息相关联的定时复杂性，加载和/或费用。

5. 发明申请

US20080074513A1 Optical black calibration 有权
标题翻译：光学黑色校准
公开(公告)号：US20080074513A1
公开(公告)日：2008-03-27
申请号：US11525699
申请日：2006-09-21
申请人： Yasu Noguchi
发明人： Yasu Noguchi
IPC分类号： H04N9/64
CPC分类号： H04N5/361 , H04N5/372
摘要： Preview mode low-resolution readouts occur, and then a shutter button on a camera is pressed, which causes an image sensor cleanout operation to occur. Following the cleanout, a high-resolution readout occurs. As rows of sensor values are read, the first rows are rows corresponding to a pre-defined horizontally-extending shielded area. There are no valid area sensor elements to either side of the horizontally-extending area. Data values read from the horizontally-extending area are used to determine optical black (OB) values that are then used to adjust the valid area values read out of the image sensor in that same frame. The same OB values are used throughout the adjusting of the valid area values of the entire frame. No values from the preview readouts are used in the OB value determination, so there is a clean break between the preview mode OB level and the high-resolution capture OB level.
摘要翻译：发生预览模式低分辨率读数，然后按下相机上的快门按钮，这将导致图像传感器清除操作发生。清理后，会发生高分辨率读数。读取传感器值行时，第一行是对应于预定义的水平延伸的屏蔽区域的行。在水平延伸区域的任一侧没有有效的区域传感器元件。从水平延伸区域读取的数据值用于确定光学黑色（OB）值，然后用于调整在同一帧中从图像传感器读出的有效面积值。在调整整个帧的有效面积值时使用相同的OB值。在OB值确定中没有使用预览读数中的值，因此在预览模式OB级别和高分辨率捕获OB级别之间存在干净的中断。

6. 发明授权

US08115835B2 Programmable digital black level calibration with feedback control 有权
标题翻译：可编程数字黑电平校准与反馈控制
公开(公告)号：US08115835B2
公开(公告)日：2012-02-14
申请号：US12290158
申请日：2008-10-27
申请人： Yasu Noguchi , Kazuya Sasaki
发明人： Yasu Noguchi , Kazuya Sasaki
IPC分类号： H04N5/217 , H04N5/64 , H04N5/335
CPC分类号： H03M1/1019 , H03M1/12 , H04N5/361 , H04N5/372
摘要： A programmable digital black level calibration circuit comprises a combining circuit, a digital programmable gain amplifier (PGA), and a black level feedback circuit. The combining circuit combines a digital image signal for optical black (OB) pixels and a feedback signal and outputs a digital PGA input signal. The PGA amplifies the digital PGA input signal by a PGA gain value and outputs a digital PGA output signal. The black level feedback circuit receives the digital PGA output signal and a target black level and in response outputs the feedback signal such that a black level of the OB pixels is calibrated with respect to the target black level. The programmable digital black level calibration circuit calibrates the black level in pure digital domain using signed data buses. The target black level is adjustable to a desired positive or negative value independent from the PGA gain value.
摘要翻译：可编程数字黑电平校准电路包括组合电路，数字可编程增益放大器（PGA）和黑电平反馈电路。组合电路组合用于光学黑（OB）像素的数字图像信号和反馈信号，并输出数字PGA输入信号。 PGA通过PGA增益值放大数字PGA输入信号，并输出数字PGA输出信号。黑电平反馈电路接收数字PGA输出信号和目标黑电平，并且作为响应输出反馈信号，使得相对于目标黑电平校准OB像素的黑电平。可编程数字黑电平校准电路使用签名数据总线校准纯数字域中的黑电平。目标黑电平可调整到所需的正值或负值，独立于PGA增益值。

7. 发明授权

US07817197B2 Optical black calibration 有权
标题翻译：光学黑色校准
公开(公告)号：US07817197B2
公开(公告)日：2010-10-19
申请号：US11525699
申请日：2006-09-21
申请人： Yasu Noguchi
发明人： Yasu Noguchi
IPC分类号： H04N9/64 , H04N3/14
CPC分类号： H04N5/361 , H04N5/372
摘要： Preview mode low-resolution readouts occur, and then a shutter button on a camera is pressed, which causes an image sensor cleanout operation to occur. Following the cleanout, a high-resolution readout occurs. As rows of sensor values are read, the first rows are rows corresponding to a pre-defined horizontally-extending shielded area. There are no valid area sensor elements to either side of the horizontally-extending area. Data values read from the horizontally-extending area are used to determine optical black (OB) values that are then used to adjust the valid area values read out of the image sensor in that same frame. The same OB values are used throughout the adjusting of the valid area values of the entire frame. No values from the preview readouts are used in the OB value determination, so there is a clean break between the preview mode OB level and the high-resolution capture OB level.
摘要翻译：发生预览模式低分辨率读数，然后按下相机上的快门按钮，这将导致图像传感器清除操作发生。清理后，会发生高分辨率读数。读取传感器值行时，第一行是对应于预定义的水平延伸的屏蔽区域的行。在水平延伸区域的任一侧没有有效的区域传感器元件。从水平延伸区域读取的数据值用于确定光学黑色（OB）值，然后用于调整在同一帧中从图像传感器读出的有效面积值。在调整整个帧的有效面积值时使用相同的OB值。在OB值确定中没有使用预览读数中的值，因此在预览模式OB级别和高分辨率捕获OB级别之间存在干净的中断。

8. 发明授权

US07791658B2 Analog front end timing generator (AFE/TG) having a bit slice output mode 有权
标题翻译：具有位片输出模式的模拟前端定时发生器（AFE / TG）
公开(公告)号：US07791658B2
公开(公告)日：2010-09-07
申请号：US11044379
申请日：2005-01-27
申请人： Yasu Noguchi
发明人： Yasu Noguchi
IPC分类号： H04N9/09
CPC分类号： H04N5/335
摘要： A versatile analog front end and timing generator (AFE/TG) integrated circuit has output modes wherein multiple identical AFE/TGs output digitized sensor data to a single digital image processor (DIP) without intervening discrete multiplexing circuitry. In one embodiment, the AFE/TG is operable in either a bit slice mode or a time slice mode. In the bit slice mode, each of the multiple AFE/TGs sections up a word of pixel information into subsets of bits, and then communicates the subsets in parallel, one subset after another, across point-to-point connections to corresponding terminals of the DIP. The DIP captures the subsets of bits, and reassembles the subsets to recreate the word of pixel information. Each of the multiple AFE/TGs communicates words of pixel information to a different set of terminals on the DIP in this way, thereby avoiding timing complications, loading and/or expense associated with communicating the pixel information using time multiplexing techniques.
摘要翻译：多功能模拟前端和定时发生器（AFE / TG）集成电路具有输出模式，其中多个相同的AFE / TG将数字化传感器数据输出到单个数字图像处理器（DIP），而无需插入离散复用电路。在一个实施例中，AFE / TG可以在位片模式或时间片模式中操作。在比特片模式中，多个AFE / TG中的每一个将像素信息的字段分成比特的子集，然后并行地将一个子集并行地通过点到多个点连接到对应的终端蘸。 DIP捕获位的子集，并重新组合子集以重新创建像素信息的单词。多个AFE / TG中的每一个以这种方式将像素信息的字传送到DIP上的不同终端集合，从而避免与使用时间复用技术传送像素信息相关联的定时复杂性，加载和/或费用。

9. 发明申请

US20090059012A1 Programmable digital black level calibration with feedback control 有权
标题翻译：可编程数字黑电平校准与反馈控制
公开(公告)号：US20090059012A1
公开(公告)日：2009-03-05
申请号：US12290158
申请日：2008-10-27
申请人： Yasu Noguchi , Kazuya Sasaki
发明人： Yasu Noguchi , Kazuya Sasaki
IPC分类号： H04N17/00 , H03M1/12
CPC分类号： H03M1/1019 , H03M1/12 , H04N5/361 , H04N5/372
摘要： A programmable digital black level calibration circuit comprises a combining circuit, a digital programmable gain amplifier (PGA), and a black level feedback circuit. The combining circuit combines a digital image signal for optical black (OB) pixels and a feedback signal and outputs a digital PGA input signal. The PGA amplifies the digital PGA input signal by a PGA gain value and outputs a digital PGA output signal. The black level feedback circuit receives the digital PGA output signal and a target black level and in response outputs the feedback signal such that a black level of the OB pixels is calibrated with respect to the target black level. The programmable digital black level calibration circuit calibrates the black level in pure digital domain using signed data buses. The target black level is adjustable to a desired positive or negative value independent from the PGA gain value.
摘要翻译：可编程数字黑电平校准电路包括组合电路，数字可编程增益放大器（PGA）和黑电平反馈电路。组合电路组合用于光学黑（OB）像素的数字图像信号和反馈信号，并输出数字PGA输入信号。 PGA通过PGA增益值放大数字PGA输入信号，并输出数字PGA输出信号。黑电平反馈电路接收数字PGA输出信号和目标黑电平，并且作为响应输出反馈信号，使得相对于目标黑电平校准OB像素的黑电平。可编程数字黑电平校准电路使用签名数据总线校准纯数字域中的黑电平。目标黑电平可调整到所需的正值或负值，独立于PGA增益值。

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