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1. 发明申请

US20060044891A1 Memory system and method for strobing data, command and address signals 有权
公开(公告)号：US20060044891A1
公开(公告)日：2006-03-02
申请号：US10931472
申请日：2004-08-31
申请人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
发明人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222
摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

2. 发明授权

US06930955B2 Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM 失效
标题翻译：用于在高速DRAM中建立和维持期望的读延迟的方法和装置
公开(公告)号：US06930955B2
公开(公告)日：2005-08-16
申请号：US10851081
申请日：2004-05-24
申请人： Brian Johnson , Brent Keeth , Feng Lin
发明人： Brian Johnson , Brent Keeth , Feng Lin
IPC分类号： G11C7/10 , G11C7/22 , G11C8/00 , G11C11/4076
CPC分类号： G11C7/222 , G11C7/1072 , G11C11/4076
摘要： A method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal in order to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve a specified read latency. A reset signal is generated at DRAM initialization and starts an first counter, which counts external clock cycles, and is also passed through the slave delay line of the delay lock loop to start a second counter. The counters run continuously once started and the difference in count values represent the internal delay as an external clock signal passes through the delay lock loop to produce an internal read clock signal. An internal read latency value is used to offset either counter to account for the internal read latency of the DRAM circuit. Once the non-offset counter is equivalent to the offset counter, read data is placed on an output line with a specified read latency and synchronized with the external read clock.
摘要翻译：一种用于管理从外部时钟信号导出的内部时钟信号的可变定时的方法和装置，以便补偿相对于数据流的读取时钟反馈时序的不确定性和变化，以实现指定的读取等待时间。在DRAM初始化时产生复位信号，并启动计数外部时钟周期的第一计数器，并且还通过延迟锁定循环的从延迟线来启动第二个计数器。一旦启动，计数器连续运行，当外部时钟信号通过延迟锁定环路以产生内部读取时钟信号时，计数值的差异代表内部延迟。内部读延迟值用于抵消DRAM电路的内部读延迟。一旦非偏移计数器等效于偏移计数器，读取数据将放置在具有指定读延迟并与外部读时钟同步的输出线上。

3. 发明授权

US07269094B2 Memory system and method for strobing data, command and address signals 有权
公开(公告)号：US07269094B2
公开(公告)日：2007-09-11
申请号：US11352131
申请日：2006-02-10
申请人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
发明人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222
摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

4. 发明申请

US20060126406A1 Memory system and method for strobing data, command and address signals 有权
公开(公告)号：US20060126406A1
公开(公告)日：2006-06-15
申请号：US11352142
申请日：2006-02-10
申请人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
发明人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222
摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

5. 发明授权

US06762974B1 Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM 失效
标题翻译：用于在高速DRAM中建立和维持期望的读延迟的方法和装置
公开(公告)号：US06762974B1
公开(公告)日：2004-07-13
申请号：US10389807
申请日：2003-03-18
申请人： Brian Johnson , Brent Keeth , Feng Lin
发明人： Brian Johnson , Brent Keeth , Feng Lin
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/1072 , G11C11/4076
摘要： A method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal in order to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve a specified read latency. A reset signal is generated at DRAM initialization and starts an first counter, which counts external clock cycles, and is also passed through the slave delay line of the delay lock loop to start a second counter. The counters run continuously once started and the difference in count values represent the internal delay as an external clock signal passes through the delay lock loop to produce an internal read clock signal. An internal read latency value is used to offset either counter to account for the internal read latency of the DRAM circuit. Once the non-offset counter is equivalent to the offset counter, read data is placed on an output line with a specified read latency and synchronized with the external read clock.
摘要翻译：一种用于管理从外部时钟信号导出的内部时钟信号的可变定时的方法和装置，以便补偿相对于数据流的读取时钟反馈时序的不确定性和变化，以实现指定的读取等待时间。在DRAM初始化时产生复位信号，并启动计数外部时钟周期的第一计数器，并且还通过延迟锁定循环的从延迟线来启动第二个计数器。一旦启动，计数器连续运行，当外部时钟信号通过延迟锁定环路以产生内部读取时钟信号时，计数值的差异代表内部延迟。内部读延迟值用于抵消DRAM电路的内部读延迟。一旦非偏移计数器等效于偏移计数器，读取数据将放置在具有指定读延迟并与外部读时钟同步的输出线上。

6. 发明授权

US06687185B1 Method and apparatus for setting and compensating read latency in a high speed DRAM 有权
标题翻译：用于设置和补偿高速DRAM中读取延迟的方法和装置
公开(公告)号：US06687185B1
公开(公告)日：2004-02-03
申请号：US10230221
申请日：2002-08-29
申请人： Brent Keeth , Brian Johnson , Feng Lin
发明人： Brent Keeth , Brian Johnson , Feng Lin
IPC分类号： G11C800
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1066 , G11C11/4076 , G11C2207/2281
摘要： An apparatus and method for coordinating the variable timing of internal clock signals derived from an external clock signal to ensure that read data and a read clock used to latch the read data arrive at the data latch in synchronism and with a specified read latency. A read clock is produced from the external clock signal in a delay lock loop circuit and a start signal, produced in response to a read command, is passed through a delay circuit slaved with the delay lock loop so that the read clock signal and a delayed start signal are subject to the same internal timing variations. The delayed start signal is used to thereby control the output of read data by the read clock signal.
摘要翻译：一种用于协调从外部时钟信号导出的内部时钟信号的可变定时的装置和方法，以确保读取数据和用于锁存读取数据的读取时钟同步并以指定的读取延迟到达数据锁存器。在延迟锁定环路电路中，从外部时钟信号产生读时钟，并且响应于读命令产生的起始信号通过与延迟锁定环相对应的延迟电路，使得读时钟信号和延迟启动信号受到相同的内部时序变化。延迟启动信号用于通过读时钟信号控制读数据的输出。

7. 发明授权

US07245553B2 Memory system and method for strobing data, command and address signals 有权
公开(公告)号：US07245553B2
公开(公告)日：2007-07-17
申请号：US11352142
申请日：2006-02-10
申请人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
发明人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222
摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

8. 发明申请

US20060143491A1 Memory system and method for strobing data, command and address signals 有权
公开(公告)号：US20060143491A1
公开(公告)日：2006-06-29
申请号：US11352131
申请日：2006-02-10
申请人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
发明人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
IPC分类号： G06F1/12 , G06F1/06 , G06F1/04 , G11C7/10 , G11C8/00 , G06F13/42
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222
摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

9. 发明授权

US07187617B2 Memory system and method for strobing data, command and address signals 有权
公开(公告)号：US07187617B2
公开(公告)日：2007-03-06
申请号：US11351836
申请日：2006-02-10
申请人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
发明人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222
摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

10. 发明授权

US06836166B2 Method and system for delay control in synchronization circuits 失效
标题翻译：同步电路延时控制方法与系统
公开(公告)号：US06836166B2
公开(公告)日：2004-12-28
申请号：US10339752
申请日：2003-01-08
申请人： Feng Lin , Brent Keeth , Brian Johnson
发明人： Feng Lin , Brent Keeth , Brian Johnson
IPC分类号： H03L706
CPC分类号： G11C7/222 , G11C7/1072 , H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A synchronization circuit includes a first and second phase-shifting path circuit, with each generates a phase-shifted signal responsive to an input signal and the phase-shifted signal having respective fine and coarse phase shifts relative to the input signal. Each phase-shifting path circuit adjusts the coarse and fine phase shifts responsive to control signals. A selection circuit outputs one of the phase-shifted signals responsive to a selection signal. A control circuit monitors a phase shift between the input signal and the output phase-shifted signal and develops the selection and control signals to select one of the phase-shifting path circuits and to adjust the fine phase shift of the selected path circuit and the fine and coarse phase shifts of the other path circuit. When the fine delay of the selected phase-shifting path circuit has a threshold value, the control circuit develops the selection signal to select the other phase-shifting circuit.
摘要翻译：同步电路包括第一和第二移相路径电路，每个产生响应于输入信号的相移信号，并且相移信号相对于输入信号具有相应的精细和粗略的相移。每个移相路径电路响应于控制信号调整粗略和精细的相移。选择电路响应于选择信号输出一个相移信号。控制电路监视输入信号和输出相移信号之间的相移，并产生选择和控制信号以选择一个相移路径电路并调整所选路径电路的精细相移和精细和另一路径电路的粗相移。当所选择的移相路径电路的精细延迟具有阈值时，控制电路产生选择信号以选择另一个移相电路。

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