专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130314119A1 TESTING STRUCTURE AND METHOD OF USING THE TESTING STRUCTURE 有权
标题翻译：测试结构和使用测试结构的方法
公开(公告)号：US20130314119A1
公开(公告)日：2013-11-28
申请号：US13478137
申请日：2012-05-23
申请人： Fen Chen , Kai Di Feng , Pui Ling Yee
发明人： Fen Chen , Kai Di Feng , Pui Ling Yee
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , H01L2924/00 , H01L2924/0002
摘要： A metal-to-metal leakage and breakdown testing structure for semiconductor structures and method of using the testing structure is disclosed. The testing structure includes plurality of resistor bridges connected to respective two terminal devices. The testing structure further includes a plurality of switches each having a voltage node provided between resistors of a respective one of the plurality of resistor bridges. The voltage node is read at a circuit pad when a respective one of the plurality of switches is in an on state. The testing structure further includes a device turning on and off each of the plurality of switches, individually.
摘要翻译：公开了一种用于半导体结构的金属 - 金属泄漏和击穿测试结构以及使用该测试结构的方法。测试结构包括连接到相应的两个终端设备的多个电阻桥。测试结构还包括多个开关，每个开关具有设置在多个电阻器桥中的相应一个的电阻器之间的电压节点。当多个开关中的相应一个开关处于导通状态时，在电路板处读取电压节点。测试结构还包括单独地打开和关闭多个开关中的每一个的装置。

2. 发明授权

US09013202B2 Testing structure and method of using the testing structure 有权
标题翻译：测试结构和使用测试结构的方法
公开(公告)号：US09013202B2
公开(公告)日：2015-04-21
申请号：US13478137
申请日：2012-05-23
申请人： Fen Chen , Kai Di Feng , Pui Ling Yee
发明人： Fen Chen , Kai Di Feng , Pui Ling Yee
IPC分类号： G01R31/02 , H01L21/66
CPC分类号： H01L22/34 , H01L2924/00 , H01L2924/0002
摘要： A metal-to-metal leakage and breakdown testing structure for semiconductor structures and method of using the testing structure is disclosed. The testing structure includes plurality of resistor bridges connected to respective two terminal devices. The testing structure further includes a plurality of switches each having a voltage node provided between resistors of a respective one of the plurality of resistor bridges. The voltage node is read at a circuit pad when a respective one of the plurality of switches is in an on state. The testing structure further includes a device turning on and off each of the plurality of switches, individually.
摘要翻译：公开了一种用于半导体结构的金属 - 金属泄漏和击穿测试结构以及使用该测试结构的方法。测试结构包括连接到相应的两个终端设备的多个电阻桥。测试结构还包括多个开关，每个开关具有设置在多个电阻器桥中的相应一个的电阻器之间的电压节点。当多个开关中的相应一个开关处于导通状态时，在电路板处读取电压节点。测试结构还包括单独地打开和关闭多个开关中的每一个的装置。

3. 发明授权

US08338920B2 Package integrated soft magnetic film for improvement in on-chip inductor performance 有权
标题翻译：封装集成软磁膜，用于提高片上电感性能
公开(公告)号：US08338920B2
公开(公告)日：2012-12-25
申请号：US11690682
申请日：2007-05-08
申请人： John Michael Cotte , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Nils D. Hoivik , Xuefeng Liu
发明人： John Michael Cotte , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Nils D. Hoivik , Xuefeng Liu
IPC分类号： H01L23/552
CPC分类号： H01L23/04 , H01L23/5227 , H01L23/552 , H01L23/645 , H01L24/16 , H01L24/29 , H01L24/32 , H01L2224/29101 , H01L2224/2919 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01068 , H01L2924/01075 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/19042 , H01L2924/19104 , H01L2924/19105 , H01L2924/30107 , H01L2924/00 , H01L2924/01026 , H01L2924/01028 , H01L2924/01042
摘要： An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed to the package cover by an adhesive. The magnetic material may be formed directly on the package cover by one of deposition, sputtering or spraying. The magnetic material may be affixed to the integrated circuit.
摘要翻译：集成电路封装包括具有一个或多个片上电感器的集成电路。封装盖覆盖集成电路。磁性材料设置在集成电路和封装盖之间。磁性材料可以是软磁性薄膜。磁性材料可以通过粘合剂固定到包装盖上。磁性材料可以通过沉积，溅射或喷涂之一直接形成在封装盖上。磁性材料可以固定在集成电路上。

4. 发明授权

US07930664B2 Programmable through silicon via 有权
标题翻译：可编程通过硅通孔
公开(公告)号：US07930664B2
公开(公告)日：2011-04-19
申请号：US12885727
申请日：2010-09-20
申请人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
发明人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
IPC分类号： G06F17/50
CPC分类号： H01L23/5252 , H01L21/76898 , H01L24/05 , H01L24/08 , H01L25/0657 , H01L25/50 , H01L2224/05124 , H01L2224/05147 , H01L2224/05184 , H01L2224/05573 , H01L2224/05611 , H01L2224/08146 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/10253 , H01L2924/3011 , H01L2924/00 , H01L2224/05624 , H01L2924/00014 , H01L2224/05647 , H01L2224/05684
摘要： Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.
摘要翻译：硅芯片中的硅通孔（TSV）都是可编程的和不可编程的。可编程TSV可以使用金属/绝缘体/金属结构从开放状态切换到短路状态，并且通过在多层芯片堆叠中的两个相邻芯片上的互补电路进行编程。

5. 发明申请

US20090243674A1 Fractional-N Phased-Lock-Loop (PLL) System 失效
标题翻译：分数N相位锁相环（PLL）系统
公开(公告)号：US20090243674A1
公开(公告)日：2009-10-01
申请号：US12176500
申请日：2008-07-21
申请人： Kai Di Feng
发明人： Kai Di Feng
IPC分类号： H03L7/08
CPC分类号： G06F17/5063 , G01R31/31725 , G01R31/31727
摘要： In one general embodiment, a fractional-N phased-lock-loop (PLL) structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator. The fractional-N phased-lock-loop (PLL) structure further comprises a second circuit including a second multiplexer and a second random number generator, wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit. Additional systems and structures are also presented.
摘要翻译：在一般的实施例中，分数N相位锁定环（PLL）结构包括位于集成电路上的第一电路，其中第一电路包括用于产生周期性输出信号的压控振荡器，用于控制压控振荡器，用于修改压控振荡器的输入的电荷泵，用于修改输出信号的频率的反馈路径中的分频器，第一多路复用器和第一随机数发生器。分数N相位锁定环（PLL）结构还包括包括第二多路复用器和第二随机数发生器的第二电路，其中第二电路是位于集成电路外并耦合到第一电路的可编程电路。还介绍了其他系统和结构。

6. 发明申请

US20090179323A1 LOCAL AREA SEMICONDUCTOR COOLING SYSTEM 有权
标题翻译：本地半导体冷却系统
公开(公告)号：US20090179323A1
公开(公告)日：2009-07-16
申请号：US12013653
申请日：2008-01-14
申请人： Kai Di Feng , Alvin Jose Joseph , Donald J. Papae , Xiaojin Wei
发明人： Kai Di Feng , Alvin Jose Joseph , Donald J. Papae , Xiaojin Wei
IPC分类号： H01L23/38 , H01L21/60
CPC分类号： H01L23/3677 , H01L23/38 , H01L24/48 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/73215 , H01L2224/73253 , H01L2924/00014 , H01L2924/12041 , H01L2924/14 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A system and method in which a semiconductor chip has electrically inactive metal-filled vias adjacent to a semiconductor device or devices to be cooled and the semiconductor device or devices are preferably surrounded by thermally insulating vias. The metal-filled vias are contacted with a thermoelectric cooler to remove excess heat from the semiconductor device or devices.
摘要翻译：一种系统和方法，其中半导体芯片具有与半导体器件或待冷却的器件相邻的电惰性金属填充的通孔，并且半导体器件或器件优选地被隔热通孔包围。金属填充的通孔与热电冷却器接触以从半导体器件或器件去除多余的热量。

7. 发明授权

US07250778B2 Wafer test apparatus including optical elements and method of using the test apparatus 有权
标题翻译：包括光学元件的晶片测试装置和使用该测试装置的方法
公开(公告)号：US07250778B2
公开(公告)日：2007-07-31
申请号：US11006184
申请日：2004-12-07
申请人： Kai Di Feng
发明人： Kai Di Feng
IPC分类号： G01R31/302 , G01R31/28
CPC分类号： H04B10/07 , G01R31/311 , H04B10/505
摘要： Wafer-level testing is performed on an electronic device to be used in an optical communications system. An optical test signal is generated and is provided to a first photo detector. An electrical output of the first photo detector is supplied to the electronic device on the wafer. An electrical output from the electronic device on the wafer is used to drive a light source. An optical output of the light source is supplied to a second photo detector and an electrical signal output from the second photo detector is examined.
摘要翻译：在光通信系统中使用的电子设备上执行晶片级测试。生成光学测试信号并提供给第一光电检测器。第一光电检测器的电输出被提供给晶片上的电子器件。来自晶片上的电子设备的电输出用于驱动光源。光源的光输出被提供给第二光检测器，并检查从第二光检测器输出的电信号。

8. 发明授权

US07061359B2 On-chip inductor with magnetic core 有权
标题翻译：带磁芯的片上电感
公开(公告)号：US07061359B2
公开(公告)日：2006-06-13
申请号：US10604180
申请日：2003-06-30
申请人： Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01F5/00
CPC分类号： H01F41/046 , H01F17/0006 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An inductor formed on an integrated circuit chip including one or more inner layers (12) between two or more outer layers (14), inductor metal winding turns (16) included in one or more inner layers (12), and a magnetic material forming the two or more outer layers (14) and the one or more inner layers (12). In one embodiment, the magnetic material is a photoresist paste having magnetic particles. In another embodiment, the magnetic material is a series of magnetic metallic strips (32 and 36) disposed on each of the first and second portions (30 and 34, respectively) of the two or more outer layers (14) and on each of the one or more inner layers (12). The series of magnetic metallic strips on the first and second portions (30, 34) form a grid pattern. Other embodiments include an adjustable controlled compound deposit and control windings with adjustable electrical currents.
摘要翻译：形成在集成电路芯片上的电感器，其包括在一个或多个内层（12）中包括的两个或多个外层（14），电感器金属绕组匝（16）之间的一个或多个内层（12）两个或多个外层（14）和一个或多个内层（12）。在一个实施例中，磁性材料是具有磁性颗粒的光致抗蚀剂浆料。在另一个实施例中，磁性材料是一系列设置在两个或多个外层（14）的第一和第二部分（30和34）的每一个上的磁性金属条（32和36）一个或多个内层（12）。第一和第二部分（30,34）上的一系列磁性金属条形成网格图案。其他实施例包括具有可调电流的可调控制的化合物沉积和控制绕组。

9. 发明授权

US06700424B2 Multiple-channel optical transceiver input buffer with zero static current and symmetrical hysteresis 失效
标题翻译：具有零静态电流和对称滞后的多通道光收发器输入缓冲器
公开(公告)号：US06700424B2
公开(公告)日：2004-03-02
申请号：US09682044
申请日：2001-07-13
申请人： Kai Di Feng
发明人： Kai Di Feng
IPC分类号： H03K3037
CPC分类号： H03K3/3565 , H03K17/223
摘要： An input buffer for an optical receiver or transceiver which provides symmetrical hysteresis and zero static current, comprises two field effect transistors (FETs) which form the basic buffer logic circuit, two FETs which respectively provide offset voltages to the buffer logic FETs, and two FETs which provide positive feedback. In the preferred embodiment the input buffer provides multiple-channels, each channel comprising a component inverter designed to provide zero static current and symmetrical hysteresis for a different input signal mode.
摘要翻译：用于提供对称滞后和零静态电流的光接收器或收发器的输入缓冲器包括形成基本缓冲逻辑电路的两个场效应晶体管（FET），分别向缓冲逻辑FET提供偏置电压的两个FET和两个FET 这提供了积极的反馈。在优选实施例中，输入缓冲器提供多通道，每个通道包括被设计成为不同的输入信号模式提供零静态电流和对称滞后的分量反相器。

10. 发明授权

US06175434B1 Adaptive infrared communication apparatus 失效
标题翻译：自适应红外通信设备
公开(公告)号：US06175434B1
公开(公告)日：2001-01-16
申请号：US08993298
申请日：1997-12-18
申请人： Kai Di Feng
发明人： Kai Di Feng
IPC分类号： H04B1000
CPC分类号： H04B10/2513
摘要： An infrared communication device with an adaptive configuration controller for programming system parameter settings with command codes. The adaptive configuration controller comprises a number of shift registers and control circuits. The registers store command codes for configuring system parameters including bandwidth, sensitivity and LED drive current. The codes are obtained from an external source. The capability to program the system parameter settings allows the communication device to be adapted or reconfigured for optimal operation in response to changes in the environment without the need for removing or adding external components.
摘要翻译：具有自适应配置控制器的红外通信设备，用于使用命令代码编程系统参数设置。自适应配置控制器包括多个移位寄存器和控制电路。寄存器存储用于配置系统参数的命令代码，包括带宽，灵敏度和LED驱动电流。代码是从外部来源获得的。对系统参数设置进行编程的功能允许通信设备被调整或重新配置，以便响应于环境变化而进行最佳操作，而无需移除或添加外部组件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式