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1. 发明授权

US07855443B2 Stack structure of semiconductor packages and method for fabricating the stack structure 有权
标题翻译：半导体封装的堆叠结构和制造堆叠结构的方法
公开(公告)号：US07855443B2
公开(公告)日：2010-12-21
申请号：US11732853
申请日：2007-04-04
申请人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
发明人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
IPC分类号： H01L23/02
CPC分类号： H01L25/105 , H01L23/49811 , H01L23/49838 , H01L24/73 , H01L25/50 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/01077 , H01L2924/15311 , H01L2924/15331 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.
摘要翻译：提供半导体封装的堆叠结构以及制造叠层结构的方法。在上半导体封装的衬底的表面上和与下半导体封装的密封剂周围的位置对应的位置处形成多个电连接焊盘和虚拟焊盘。将焊球植入电连接焊盘和虚拟焊盘。上半导体封装安装在下半导体封装上。上半导体封装通过注入电连接焊盘的焊球电连接到下半导体封装，并且下半导体封装的密封剂被植入到虚拟焊盘中的焊球围绕并限制。因此，上半导体封装被适当且牢固地定位在下半导体封装上，而不会发生上下半导体封装之间的未对准。

2. 发明授权

US08420521B2 Method for fabricating stack structure of semiconductor packages 有权
标题翻译：制造半导体封装的堆叠结构的方法
公开(公告)号：US08420521B2
公开(公告)日：2013-04-16
申请号：US12955256
申请日：2010-11-29
申请人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
发明人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
IPC分类号： H01L21/44
CPC分类号： H01L25/105 , H01L23/49811 , H01L23/49838 , H01L24/73 , H01L25/50 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/01077 , H01L2924/15311 , H01L2924/15331 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.
摘要翻译：提供半导体封装的堆叠结构以及制造叠层结构的方法。在上半导体封装的衬底的表面上和与下半导体封装的密封剂周围的位置对应的位置处形成多个电连接焊盘和虚拟焊盘。将焊球植入电连接焊盘和虚拟焊盘。上半导体封装安装在下半导体封装上。上半导体封装通过注入电连接焊盘的焊球电连接到下半导体封装，并且下半导体封装的密封剂被植入到虚拟焊盘中的焊球围绕并限制。因此，上半导体封装被适当且牢固地定位在下半导体封装上，而不会发生上下半导体封装之间的未对准。

3. 发明申请

US20070246811A1 Stack structure of semiconductor packages and method for fabricating the stack structure 有权
标题翻译：半导体封装的堆叠结构和制造堆叠结构的方法
公开(公告)号：US20070246811A1
公开(公告)日：2007-10-25
申请号：US11732853
申请日：2007-04-04
申请人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
发明人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
IPC分类号： H01L23/02 , H01L21/00
CPC分类号： H01L25/105 , H01L23/49811 , H01L23/49838 , H01L24/73 , H01L25/50 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/01077 , H01L2924/15311 , H01L2924/15331 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.
摘要翻译：提供半导体封装的堆叠结构以及制造叠层结构的方法。在上半导体封装的衬底的表面上和与下半导体封装的密封剂周围的位置对应的位置处形成多个电连接焊盘和虚拟焊盘。将焊球植入电连接焊盘和虚拟焊盘。上半导体封装安装在下半导体封装上。上半导体封装通过注入电连接焊盘的焊球电连接到下半导体封装，并且下半导体封装的密封剂被植入到虚拟焊盘中的焊球围绕并限制。因此，上半导体封装被适当且牢固地定位在下半导体封装上，而不会发生上下半导体封装之间的未对准。

4. 发明申请

US20110070697A1 METHOD FOR FABRICATING STACK STRUCTURE OF SEMICONDUCTOR PACKAGES 有权
标题翻译：用于制作半导体封装的堆叠结构的方法
公开(公告)号：US20110070697A1
公开(公告)日：2011-03-24
申请号：US12955256
申请日：2010-11-29
申请人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
发明人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
IPC分类号： H01L21/48
CPC分类号： H01L25/105 , H01L23/49811 , H01L23/49838 , H01L24/73 , H01L25/50 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/01077 , H01L2924/15311 , H01L2924/15331 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.
摘要翻译：提供半导体封装的堆叠结构以及制造叠层结构的方法。在上半导体封装的衬底的表面上和与下半导体封装的密封剂周围的位置相对应的位置处形成多个电连接焊盘和虚拟焊盘。将焊球植入电连接焊盘和虚拟焊盘。上半导体封装安装在下半导体封装上。上半导体封装通过注入电连接焊盘的焊球电连接到下半导体封装，并且下半导体封装的密封剂被植入到虚拟焊盘中的焊球围绕并限制。因此，上半导体封装被适当且牢固地定位在下半导体封装上，而不会发生上下半导体封装之间的未对准。

5. 发明申请

US20070202633A1 Semiconductor package and method for fabricating the same 审中-公开
标题翻译：半导体封装及其制造方法
公开(公告)号：US20070202633A1
公开(公告)日：2007-08-30
申请号：US11651708
申请日：2007-01-09
申请人： Wen-Tsung Tseng , Fang-Lin Tsai , Ho-Yi Tsai , Cheng-Hsu Hsiao , Chih-Ming Huang
发明人： Wen-Tsung Tseng , Fang-Lin Tsai , Ho-Yi Tsai , Cheng-Hsu Hsiao , Chih-Ming Huang
IPC分类号： H01L21/00
CPC分类号： H01L21/4882 , H01L23/3675 , H01L23/544 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2223/5442 , H01L2223/54473 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/01079 , H01L2924/16152 , H01L2924/16315 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/00015
摘要： A semiconductor package and a method for fabricating the same are provided. The method includes providing a substrate having recognition points and a heat sink having openings, and placing the heat sink on the substrate with the recognition points being exposed through the openings; using a checking system to inspect the recognition points through the openings so as to ensure that the heat sink is placed at a predetermined position on the substrate; and attaching the heat sink to the substrate via an adhesive. By the above semiconductor package and method, there is no need to form positioning holes in the substrate such that any adverse effect on the circuit layout and reliability of the semiconductor package is avoided, and any positional shifting of the heat sink relative to the substrate can be determined in a real time manner.
摘要翻译：提供半导体封装及其制造方法。该方法包括提供具有识别点的基板和具有开口的散热器，并且将散热器放置在基板上，识别点通过开口露出; 使用检查系统通过开口检查识别点，以确保散热器被放置在基板上的预定位置; 以及通过粘合剂将散热器附接到基板。通过上述半导体封装和方法，不需要在衬底中形成定位孔，从而避免对半导体封装的电路布局和可靠性的任何不利影响，并且散热片相对于衬底的任何位置偏移可以以实时的方式确定。

6. 发明申请

US20070138632A1 Electronic carrier board and package structure thereof 审中-公开
标题翻译：电子载板及其封装结构
公开(公告)号：US20070138632A1
公开(公告)日：2007-06-21
申请号：US11642439
申请日：2006-12-19
申请人： Fang-Lin Tsai , Ho-Yi Tsai , Chih-Ming Huang , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Fang-Lin Tsai , Ho-Yi Tsai , Chih-Ming Huang , Chien-Ping Huang , Cheng-Hsu Hsiao
IPC分类号： H01L23/34
CPC分类号： H05K3/3452 , H05K3/284 , H05K3/303 , H05K2201/0989 , H05K2201/10636 , H05K2201/10727 , H05K2201/2036 , Y02P70/611 , Y02P70/613
摘要： An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. An opening is formed in the protective layer to expose at least three sides of each of the paired bond pads. The protective layer includes at least one independent residual portion located in the opening and between the paired bond pads, such that an electronic component is mounted on the independent residual portion and electrically connected to the bond pads. A groove without a dead space is formed between the electronic component and the carrier, such that a molding compound for encapsulating the electronic component can flow through the groove to fill the opening and a space under the electronic component and encapsulate the at least three sides of each of the bond pads.
摘要翻译：提供电子载体板及其封装结构。电子载板包括载体，形成在载体上的至少一对接合焊盘和覆盖载体的保护层。在保护层中形成开口以暴露每个配对接合焊盘的至少三个侧面。保护层包括至少一个独立的残留部分，位于开口内和成对的接合焊盘之间，使得电子部件安装在独立的残留部分上并电连接到接合焊盘。在电子部件和载体之间形成没有死空间的凹槽，使得用于封装电子部件的模制化合物可以流过凹槽以填充开口和电子部件下方的空间，并将至少三个侧面每个接合垫。

7. 发明申请

US20090096115A1 Semiconductor package and method for fabricating the same 审中-公开
标题翻译：半导体封装及其制造方法
公开(公告)号：US20090096115A1
公开(公告)日：2009-04-16
申请号：US11818050
申请日：2007-06-12
申请人： Chien-Ping Huang , Han-Ping Pu , Ho-Yi Tsai
发明人： Chien-Ping Huang , Han-Ping Pu , Ho-Yi Tsai
IPC分类号： H01L23/42 , H01L21/02 , H01L23/28
CPC分类号： H01L23/4334 , H01L21/565 , H01L23/3121 , H01L24/48 , H01L2224/16 , H01L2224/4824 , H01L2224/73204 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/15311 , H01L2924/1815 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and a method for fabricating the same are disclosed. The present invention discloses mounting and electrically connecting a semiconductor chip to a chip carrier, forming an interfacial layer or a heat-dissipating member having the interfacial layer on the semiconductor chip, and forming an encapsulant for covering the semiconductor chip, the interfacial layer or the heat dissipating member. The method further includes cutting the encapsulant along edges of the interfacial layer, and removing the redundant encapsulant on the interfacial layer so as to expose the semiconductor chip or the heat-dissipating member without forming burr or heavily wearing cutting tools.
摘要翻译：公开了一种半导体封装及其制造方法。本发明公开了将半导体芯片安装并电连接到芯片载体上，在半导体芯片上形成具有界面层的界面层或散热构件，并形成用于覆盖半导体芯片，界面层或散热构件该方法还包括沿着界面层的边缘切割密封剂，以及去除界面层上的冗余密封剂，以便露出半导体芯片或散热构件，而不会形成毛刺或严重磨损的切削工具。

8. 发明申请

US20070296079A1 Heat dissipating structure and method for fabricating the same 审中-公开
标题翻译：散热结构及其制造方法
公开(公告)号：US20070296079A1
公开(公告)日：2007-12-27
申请号：US11818225
申请日：2007-06-12
申请人： Chien-Ping Huang , Han-Ping Pu , Ho-Yi Tsai
发明人： Chien-Ping Huang , Han-Ping Pu , Ho-Yi Tsai
IPC分类号： H01L23/34 , H01L21/58
CPC分类号： H01L23/4334 , H01L23/3121 , H01L24/48 , H01L2224/4824 , H01L2224/73204 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/1815 , H01L2924/18165 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A heat sink package structure and a method for fabricating the same are disclosed. The method includes mounting and electrically connecting a semiconductor chip to a chip carrier, forming an interface layer or a second heat dissipating element having the interface layer on the semiconductor chip and installing a first heat dissipating element having a heat dissipating portion and a supporting portion onto the chip carrier. The method further includes forming openings corresponding to the semiconductor chip in the heat dissipating portion, and forming an encapsulant for covering the semiconductor chip, the interface layer or the second heat dissipating element, and the first heat dissipating element. A height is reserved on top of the interface layer for the formation of the encapsulant for covering the interface layer. The method further includes cutting the encapsulant along edges of the interface layer, and removing the redundant encapsulant on the interface layer. Therefore, the drawbacks of the prior art of the burrs caused by a cutting tool for cutting the heat dissipating element and wearing of the cutting tool are overcome.
摘要翻译：公开了一种散热器封装结构及其制造方法。该方法包括将半导体芯片安装并电连接到芯片载体，在半导体芯片上形成具有界面层的界面层或第二散热元件，并将具有散热部分和支撑部分的第一散热元件安装到芯片载体。该方法还包括形成对应于散热部分中的半导体芯片的开口，以及形成用于覆盖半导体芯片，界面层或第二散热元件的密封剂和第一散热元件。在接口层顶部保留一个高度，用于形成覆盖界面层的密封剂。该方法还包括沿着界面层的边缘切割密封剂，以及去除界面层上的冗余密封剂。因此，克服了用于切割散热元件的切削工具和切削工具的磨损引起的毛刺现有技术的缺陷。

9. 发明申请

US20110287588A1 METHOD FOR MANUFACTURING HEAT-DISSIPATING SEMICONDUCTOR PACKAGE STRUCTURE 审中-公开
标题翻译：制造散热半导体封装结构的方法
公开(公告)号：US20110287588A1
公开(公告)日：2011-11-24
申请号：US13195639
申请日：2011-08-01
申请人： Wen-Tsung Tseng , Ho-Yi Tsai , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Wen-Tsung Tseng , Ho-Yi Tsai , Chien-Ping Huang , Cheng-Hsu Hsiao
IPC分类号： H01L21/56
CPC分类号： H01L23/4334 , H01L21/565 , H01L23/3128 , H01L23/552 , H01L24/48 , H01L25/03 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A heat-dissipating semiconductor package structure and a method for manufacturing the same is disclosed. The method includes: disposing on and electrically connecting to a chip carrier at least a semiconductor chip and a package unit; disposing on the top surface of the package unit a heat-dissipating element having a flat portion and a supporting portion via the flat portion; receiving the package unit and semiconductor chip in a receiving space formed by the flat portion and supporting portion of the heat-dissipating element; and forming on the chip carrier encapsulant for encapsulating the package unit, semiconductor chip, and heat-dissipating element. The heat-dissipating element dissipates heat generated by the package unit, provides EMI shielding, prevents delamination between the package unit and the encapsulant, decreases thermal resistance, and prevents cracking.
摘要翻译：公开了一种散热半导体封装结构及其制造方法。该方法包括：在至少半导体芯片和封装单元上布置并电连接到芯片载体; 在所述封装单元的顶表面上设置有经由所述平坦部分具有平坦部分和支撑部分的散热元件; 在由散热元件的平坦部分和支撑部分形成的接收空间中接收封装单元和半导体芯片; 以及在芯片载体密封剂上形成以封装封装单元，半导体芯片和散热元件。散热元件消散封装单元产生的热量，提供EMI屏蔽，防止封装单元与密封剂之间的分层，降低热阻，防止开裂。

10. 发明申请

US20080213942A1 Method for fabricating semiconductor device and carrier applied therein 审中-公开
标题翻译：制造应用于其中的半导体器件和载体的方法
公开(公告)号：US20080213942A1
公开(公告)日：2008-09-04
申请号：US12074321
申请日：2008-03-03
申请人： Min-Shun Hung , Ho-Yi Tsai , Chien-Ping Huang , Wen-Tsung Tseng , Cheng-Hsu Hsiao
发明人： Min-Shun Hung , Ho-Yi Tsai , Chien-Ping Huang , Wen-Tsung Tseng , Cheng-Hsu Hsiao
IPC分类号： H01L23/12 , H05K7/00
CPC分类号： H01L23/3128 , H01L21/563 , H01L21/568 , H01L21/6835 , H01L24/16 , H01L2224/13099 , H01L2224/16 , H01L2224/73203 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/00 , H01L2224/0401
摘要： This invention provides a method for fabricating a semiconductor device and a carrier applied therein. The method includes the steps of: disposing a chip-mounted substrate in an opening of a carrier; forming at least a storage aperture and at least an inspection aperture in the carrier; infusing an adhesive into the storage aperture to fill a gap between the substrate and carrier with the adhesive by capillarity; determining whether the inspection aperture is filled with the adhesive to ascertain whether the gap is completely filled with the adhesive; in response to a positive result, performing a molding process to form a molding compound for encapsulating the chip; and performing implantation of solder ball and a singulation process to form a semiconductor device with desirable dimensions. The inspection aperture is inspected with a naked eye to determine whether the gap is completely filled with the adhesive, thereby reducing inspection costs and increasing yields of products with no additional packaging costs.
摘要翻译：本发明提供一种用于制造应用于其中的半导体器件和载体的方法。该方法包括以下步骤：将芯片安装的基板设置在载体的开口中; 在所述载体中至少形成存储孔径和至少一个检查孔; 将粘合剂注入到存储孔中，以通过毛细管力用粘合剂填充基底和载体之间的间隙; 确定检查孔是否填充有粘合剂以确定间隙是否完全被粘合剂填充; 响应于积极的结果，进行成型处理以形成用于封装芯片的模塑料; 并且执行焊球的注入和单一化处理以形成具有所需尺寸的半导体器件。检查孔径用肉眼检查以确定间隙是否完全充满粘合剂，从而降低检查成本并提高产品的产量，而不需要额外的包装成本。

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