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1. 发明授权

US07646108B2 Multiple output voltage regulator 失效
标题翻译：多输出电压调节器
公开(公告)号：US07646108B2
公开(公告)日：2010-01-12
申请号：US11537046
申请日：2006-09-29
申请人： Fabrice Paillet , Nick Triantafillou , Azam Barkatullah , Daniel Elmhurst , Peter Harrington , Raymond W. Zeng
发明人： Fabrice Paillet , Nick Triantafillou , Azam Barkatullah , Daniel Elmhurst , Peter Harrington , Raymond W. Zeng
IPC分类号： H02J1/00 , G05F1/10 , G05F1/577
CPC分类号： H02M3/158 , H02M2001/008 , Y10T307/25
摘要： Some embodiments include a die having an output control circuit to interact with an output circuit to convert a source voltage into at least one output voltage. The die may also have a converter circuit to convert the output voltage into at least one additional output voltage.
摘要翻译：一些实施例包括具有与输出电路相互作用以将源电压转换成至少一个输出电压的输出控制电路的管芯。芯片还可以具有转换器电路，以将输出电压转换成至少一个额外的输出电压。

2. 发明申请

US20080080103A1 MULTIPLE OUTPUT VOLTAGE REGULATOR 失效
标题翻译：多路输出稳压器
公开(公告)号：US20080080103A1
公开(公告)日：2008-04-03
申请号：US11537046
申请日：2006-09-29
申请人： Fabrice Paillet , Nick Triantafillou , Azam Barkatullah , Daniel Elmhurst , Peter Harrington , Raymond W. Zeng
发明人： Fabrice Paillet , Nick Triantafillou , Azam Barkatullah , Daniel Elmhurst , Peter Harrington , Raymond W. Zeng
IPC分类号： H02H7/00
CPC分类号： H02M3/158 , H02M2001/008 , Y10T307/25
摘要： Some embodiments include a die having an output control circuit to interact with an output circuit to convert a source voltage into at least one output voltage. The die may also have a converter circuit to convert the output voltage into at least one additional output voltage.
摘要翻译：一些实施例包括具有与输出电路相互作用以将源电压转换成至少一个输出电压的输出控制电路的管芯。芯片还可以具有转换器电路，以将输出电压转换成至少一个额外的输出电压。

3. 发明授权

US09747977B2 Methods and systems for verifying cell programming in phase change memory 有权
公开(公告)号：US09747977B2
公开(公告)日：2017-08-29
申请号：US13827825
申请日：2013-03-14
申请人： Daniel J. Chu , Raymond W. Zeng , Doyle Rivers
发明人： Daniel J. Chu , Raymond W. Zeng , Doyle Rivers
IPC分类号： G11C11/56 , G11C16/34 , G11C16/10 , G11C13/00
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/0064 , G11C13/0069
摘要： Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.

4. 发明授权

US07319616B2 Negatively biasing deselected memory cells 有权
标题翻译：负偏置取消选择的存储单元
公开(公告)号：US07319616B2
公开(公告)日：2008-01-15
申请号：US10713841
申请日：2003-11-13
申请人： Rajesh Sundaram , Jahanshir Javanifard , Kerry D. Tedrow , Priya Walimbe , Tom H. Ly , Raymond W. Zeng
发明人： Rajesh Sundaram , Jahanshir Javanifard , Kerry D. Tedrow , Priya Walimbe , Tom H. Ly , Raymond W. Zeng
IPC分类号： G11C16/06
CPC分类号： G11C16/08 , G11C8/08
摘要： In one embodiment, the present invention includes a method to supply a negative voltage to at least one deselected wordline of a memory array. Further, while the negative voltage is supplied to deselected wordlines, a positive voltage may be supplied to a selected wordline. The memory array may be a flash memory incorporating multi-level cell architecture, in one embodiment.
摘要翻译：在一个实施例中，本发明包括将负电压提供给存储器阵列的至少一个未选择的字线的方法。此外，当将负电压提供给未选择的字线时，可以向所选择的字线提供正电压。在一个实施例中，存储器阵列可以是并入多级单元架构的闪速存储器。

5. 发明授权

US06836176B2 Charge pump ripple reduction 有权
标题翻译：电荷泵波动减小
公开(公告)号：US06836176B2
公开(公告)日：2004-12-28
申请号：US10185419
申请日：2002-06-27
申请人： Raymond W. Zeng , Ravi P. Annavajjhala , Mary Frances Therese B. Yuvienco
发明人： Raymond W. Zeng , Ravi P. Annavajjhala , Mary Frances Therese B. Yuvienco
IPC分类号： G05F1576
CPC分类号： H02M3/073 , H02M2003/077
摘要： A charge pump control circuit may include a frequency synthesis device, a pump cell connected to the frequency synthesis device, and a feedforward circuit connected to the frequency synthesis device to selectively activate or deactivate the frequency synthesis device in response to a pump cell output signal.
摘要翻译：电荷泵控制电路可以包括频率合成装置，连接到频率合成装置的泵浦单元和连接到频率合成装置的前馈电路，以响应于泵浦单元输出信号选择性地激活或去激活频率合成装置。

6. 发明授权

US08681540B2 Tile-level snapback detection through coupling capacitor in a cross point array 有权
标题翻译：通过在交叉点阵列中耦合电容器进行平铺级快速回发检测
公开(公告)号：US08681540B2
公开(公告)日：2014-03-25
申请号：US13466999
申请日：2012-05-08
申请人： Raymond W. Zeng
发明人： Raymond W. Zeng
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C13/0061
摘要： Embodiments of the present disclosure describe methods, apparatus, and system configurations for tile-level snapback detection through a coupling capacitor in a phase-change memory array. Other embodiments may be described and claimed.
摘要翻译：本公开的实施例描述了通过相变存储器阵列中的耦合电容器进行瓦片级快速恢复检测的方法，装置和系统配置。可以描述和要求保护其他实施例。

7. 发明授权

US08462577B2 Single transistor driver for address lines in a phase change memory and switch (PCMS) array 有权
标题翻译：单相晶体管驱动器，用于相变存储器和开关（PCMS）阵列中的地址线
公开(公告)号：US08462577B2
公开(公告)日：2013-06-11
申请号：US13051800
申请日：2011-03-18
申请人： Raymond W. Zeng , DerChang Kau
发明人： Raymond W. Zeng , DerChang Kau
IPC分类号： G11C8/00
CPC分类号： G11C16/06 , G11C8/08 , G11C8/18 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C16/08
摘要： The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, a single transistor may be used to drive each address line, either a wordline or a bitline. Both an inhibit voltage and a selection voltage may be driven through these single transistor devices, which may be achieved with the introduction of odd and even designations for the address lines. In one operating embodiment, a selected address line may be driven to a selection voltage, and the address lines of the odd or even designation which is the same as the selected address line are allowed to float. The address lines of the odd or even designation with is different from the selected address lines are driven to an inhibit voltage, wherein adjacent floating address lines may act as shielding lines to the selected address line.
摘要翻译：本公开涉及非易失性存储器件的制造。在至少一个实施例中，可以使用单个晶体管来驱动每个地址线，字线或位线。可以通过这些单晶体管器件驱动抑制电压和选择电压，这可以通过引入用于地址线的奇数和偶数名称来实现。在一个操作实施例中，可以将所选择的地址线驱动到选择电压，并且允许与所选地址线相同的奇数或偶数指定的地址线浮动。与选择的地址线不同的奇数或偶数名称的地址线被驱动到禁止电压，其中相邻的浮动地址线可以用作到所选地址线的屏蔽线。

8. 发明授权

US07317346B2 Selecting a bias for a level shifting device 有权
标题翻译：选择电平移位装置的偏置
公开(公告)号：US07317346B2
公开(公告)日：2008-01-08
申请号：US11076970
申请日：2005-03-11
申请人： Daniel J. Chu , Raymond W. Zeng
发明人： Daniel J. Chu , Raymond W. Zeng
IPC分类号： H02J1/00
CPC分类号： G11C29/12 , G05F3/205 , G11C5/147 , G11C29/12005
摘要： One or more MOS devices may be used as a bias selecting circuit to pass a bias voltage from a bias generator to a level shifting circuit.
摘要翻译：可以使用一个或多个MOS器件作为偏置选择电路，以将偏置电压从偏置发生器传递到电平移位电路。

9. 发明申请

US20140269045A1 CELL PROGRAMMING VERIFICATION 有权
标题翻译：细胞编程验证
公开(公告)号：US20140269045A1
公开(公告)日：2014-09-18
申请号：US13827825
申请日：2013-03-14
申请人： Daniel J. Chu , Raymond W. Zeng , Doyle Rivers
发明人： Daniel J. Chu , Raymond W. Zeng , Doyle Rivers
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/0064 , G11C13/0069
摘要： Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.
摘要翻译：公开了用于验证相变存储器阵列的单元编程的技术。在一个示例中，方法可以包括将复位脉冲发送到相变存储器单元。该方法还可以包括响应于跨越相变存储器单元施加第一和第二验证电压来感测相变存储器单元的阈值电压，其中第二验证电压低于第一验证电压。该方法还可以包括确定相变存储器单元的阈值电压是否低于第一或第二验证电压。

10. 发明申请

US20140016406A1 ISOLATING, AT LEAST IN PART, LOCAL ROW OR COLUMN CIRCUITRY OF MEMORY CELL BEFORE ESTABLISHING VOLTAGE DIFFERENTIAL TO PERMIT READING OF CELL 有权
标题翻译：在建立电压差异到容许读取单元之前，至少分开存储单元的本地线或列电路
公开(公告)号：US20140016406A1
公开(公告)日：2014-01-16
申请号：US13995230
申请日：2012-06-06
申请人： Doyle Rivers , Prashant S. Damle , Raymond W. Zeng
发明人： Doyle Rivers , Prashant S. Damle , Raymond W. Zeng
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C7/02 , G11C13/004
摘要： An embodiment may include local row and column circuitry that are local to a memory cell of a memory device. Either the local row circuitry or the local column circuitry may be electrically isolated, at least in part, from at least one remaining portion of the memory device during the establishing of a voltage differential between the local row circuitry and the local column circuitry that is to permit the memory cell to be read during a read of the memory cell. The read may occur subsequent to the establishing of the voltage differential. Many variations, modifications, and alternatives are possible without departing from this embodiment.
摘要翻译：实施例可以包括对存储器件的存储器单元本地的本地行和列电路。在本地行电路和本地列电路之间的电压差建立期间，本地行电路或本地列电路可以至少部分地与存储器件的至少一个剩余部分电隔离，允许在存储器单元的读取期间读取存储器单元。读取可能在建立电压差之后发生。在不脱离本实施例的情况下，可以进行许多变化，修改和替换。

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