专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS57101950A DOUBLE STORAGE DEVICE CONTROL SYSTEM 失效
公开(公告)号：JPS57101950A
公开(公告)日：1982-06-24
申请号：JP17848880
申请日：1980-12-17
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： NIHEI TOSHIHIKO , KAWANOBE TADASHI , IGAWA IKUTOSHI , AMANO YUTAKA , KANAZAWA NOBUHARU
IPC分类号： G06F12/16 , G06F11/16
摘要： PURPOSE:To detect a latent fault on the operation in its early stage, by mutually comparing and collating the display signals showing the operation in each storage device, in case of a synchronizing operation mode of a double storage device. CONSTITUTION:A memory request generated by a processing device 2 is transferred to receiving control parts 11a, 11b of storage devices 1a, 1b, and the control parts 11a, 11b decide whether this request is receivable or not. The received memory request designates a sort of operation to sequence control parts 12a, 12b through the control parts 11a, 11b, the control parts 12a, 12b start timing control parts 13a, 13b, operate memories 14a, 14b, and execute each memory operation which has been requested. On the other hand, display signals showing the operations are transferred to collating parts 15a, 15b through signal lines 16a, 16b and 17a, 17b from the control parts 12a, 12b, 13a and 13b, compared and collated, and each operation status is checked. In this case, when dissidence is detected, it is displayed on a dissidence displaying circuit.

2. 发明专利

JPS60260260A REMOTE TEST CONTROL SYSTEM 失效
公开(公告)号：JPS60260260A
公开(公告)日：1985-12-23
申请号：JP11604184
申请日：1984-06-06
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： KANAZAWA NOBUHARU , SATOU TSUTOMU , NAKAMURA YUKIO , AOKI TOSHIROU , YASUI ISAMU
IPC分类号： H04M3/26 , H04Q1/26
摘要： PURPOSE:To improve rational maintenance work by allowing an exchange located at a remote location to be conducted with a test from a maintenance station. CONSTITUTION:In testing a required part in an exchange 1 from the maintenance station, a test command from an input/output device 2-1 in a supervisory information equipment 2 to a test object of a test object exchange 1 to a data transmission line 4. A remote supervisory test equipment 3 of a test object remote station composes the test command inputted from the typewriter in the same form, inputs it from a control interface section 1-1 and starts the test and transmits the result of test to a transmission line 4. In inputting supervisory test operation information, the operation information is inputted from an operating device 2-3 and in case of the test attended with the transmission of the voice information, the test is conducted by using a test telephone device 2-5.

3. 发明专利

JPS60113560A CONSOLE ADDER 失效
公开(公告)号：JPS60113560A
公开(公告)日：1985-06-20
申请号：JP22069883
申请日：1983-11-25
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： SUZUKI TAKAO , HATANO HAJIME , IGAWA IKUTOSHI , KITAZAWA MITSURU , KANAZAWA NOBUHARU
IPC分类号： H04M3/22 , H04Q1/26
摘要： PURPOSE:To facilitate trouble countermeasures and to obtain speedy recovery by providing a console adder which transfers automatically trouble data to a normal host station by an emergency control circuit when a central processor of an unmanned electronic switching place is in trouble. CONSTITUTION:While the system of an electronic exchange, etc., is operating on on-line basis, a CPU3 executes the on-line operation under program control by a main storage device 1 and by the self-control operation of a data channel device 5 by setting a file memory device 7 and a typewriter device 8 as I/O devices. When a trouble occurs, the internal condition of the CPU3 is readout by a console adder 11 to the host station maintained by an operator, and the display data is accumulated and editted. The data is transferred through an interface 12 which is connected to the host station regarding the data as I/O data falsely, and are typed out by the host station. In the host station, the rising of an unmanned station is executed by remote-controlling by the data.

4. 发明专利

JPS56159743A EMERGENCY CONTROL CIRCUIT 失效
公开(公告)号：JPS56159743A
公开(公告)日：1981-12-09
申请号：JP6259380
申请日：1980-05-12
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： KANAZAWA NOBUHARU , SHIMOKIBA SHIYUUICHI , ENDOU AKIRA , SAKURAI YOSHIO , YASUI ISAMU
IPC分类号： G06F11/20
摘要： PURPOSE:To prevent a system from being shut down owing to a fault of an emergency control circuit, by providing emergency control circuits in a plurality corresponding to a group of central processors forming multiple constitution. CONSTITUTION:On the occurrence of a fault, emergency control circuits EMA0 and EMA1 provided corresponding to central controllers CC0 and CC1 forming double constitution are actuated at the same time, and according to the states of emergency control counters provided in circuits EMA0 and EMA1, either one of circuits EMA0 or EMA1 is used for emergency control operation. The emergency control counters are driven every time the circuits EMA0 and EMA1 are actuated, so the circuits EMA0 and EMA1 used for the emergency control operation are selected alternately. Therefore, even if one emergency control circuit EMA0 or EMA1 gets out of order due to a fault, the remaining emergancy control circuit actuates the corresponding central controller CC0 or CC1 to perform the emergency control operation, so that the system will not be stopped.

5. 发明专利

JPS60260286A SYSTEM FOR READING STATE OF PROCESSOR 失效
公开(公告)号：JPS60260286A
公开(公告)日：1985-12-23
申请号：JP11604584
申请日：1984-06-06
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO
发明人： KANAZAWA NOBUHARU , HAYASHI KIYOUJI , NAKAMURA YUKIO , SHIBUYA TADASHI
IPC分类号： H04Q3/545 , H04M3/24 , H04Q1/22
摘要： PURPOSE:To attain proper diagnosis and restoration by providing a means for detecting an abnormal signal generated when a prescribed processor is faulty and reading sequentially the internal state of each processor as well as the said prescribed processor. CONSTITUTION:A master processor MCP0 and an alternative master processor MCP1 transmit an abnormal signal to a state signal line sl when a fault takes place in the inside. A state supervisory section SPU in a console CNS supervises the signal line sl and when the abnormal signal on the signal line sl from the MCP0 is detected, it is informed to a processor section MPU. The MPU identifies the MCP0 having a fault, a processor switching section SW is set to the MCP0 to read the internal state of the MCP0. When the read is finished, the internal state of the substitution processor MCP1 and call processing processors CNP0-CNPn is read sequentially by similar processes.

6. 发明专利

JPS63233642A MONITORING DEVICE 失效
公开(公告)号：JPS63233642A
公开(公告)日：1988-09-29
申请号：JP6765987
申请日：1987-03-20
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NEC CORP , HITACHI LTD
发明人： KANAZAWA NOBUHARU , KOBAYASHI KIYOSUMI , DAIDOJI YUTAKA , ABE HIROAKI , YAMAMURA YASUKIMI
IPC分类号： H04M3/22
摘要： PURPOSE:To simplify a circuit, by concentrating the monitoring information of plural exchanges by increasing the multiplicity of time divisional multiplexing, and reading out and displaying a bit of monitoring information in a constant order after generating an address from an address signal fitted to a time slot allocated to each exchange and accumulating the monitoring information. CONSTITUTION:An address generating part 74, by generating the address of a memory part 25 on which the monitoring information is recorded at every terminal system based on the address signals sent from line control circuits 70 and 71 at every specific time slot, and sending it to the memory part 25, records the monitoring information allocated to the time slot. A display control part 75 receives the address from the address generating part 74, and sets the specified time slot other than the time slot allocated to the monitoring information as a display timing, and reads out the monitoring information of each terminal system from the memory part 25 at slow speed, for example, in the sequence of the number of the terminal system via a bus 72, and sends and displays the monitoring information on a display device. In such a way, it is possible to display the monitoring information in a constant order by a simple circuit.

7. 发明专利

JPH02109451A ANALOG COMMUNICATION LINE ACCOMMODATION SYSTEM 失效
公开(公告)号：JPH02109451A
公开(公告)日：1990-04-23
申请号：JP26319488
申请日：1988-10-19
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NEC CORP , HITACHI LTD
发明人： KANAZAWA NOBUHARU , TAKASUGI YOSHIKAZU , DAIDOJI YUTAKA , MIURA MASAMI , YAMAMURA YASUKIMI
IPC分类号： H04M3/22 , H04J3/00
摘要： PURPOSE:To revise the classification of communication line in the unit of a few lines by revising the class of accommodated communication lines in the unit of lines accommodated in an analog digital conversion means. CONSTITUTION:An analog digital conversion means 500 converters an analog signal A reached from a prescribed number of analog communication lines into a digital signal D and outputs the result to a predetermined time area. A gate means 600 receives a digital signal D outputted from plural analog digital conversion means 500 and outputs it to a digital highway 700. A control signal generating means 800 detects loaded/unloaded analog digital conversion means 500, generates a gate control signal C making the gate means 600 conductive to the time area decided in the analog digital conversion means 500 and sends the result to a gate means 600, then the class is able to be changed in the unit of lines.

8. 发明专利

JPS5528106A INFORMATION TRANSFER SYSTEM 失效
公开(公告)号：JPS5528106A
公开(公告)日：1980-02-28
申请号：JP9894178
申请日：1978-08-14
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： KANAZAWA NOBUHARU , SHINTANI HIROSHI , USHIKI TATSUO , SEO TOMIHIDE
IPC分类号： G06F13/38 , G06F3/00 , G06F15/16
摘要： PURPOSE:To transfer the information between the information processors in the information processing system with multiplex consitution, by giving shift registers as a means of serial information transfer from the information processor to two other information processors and giving two systems of transmission and reception as the transfer route. CONSTITUTION:In transferring information from the information processor 1 to 2, the transfer data is set to the shift register SRA 10. The gates 4 and 6 are active, SRA is shifted by one bit by giving shift clock to SRA 10, and the data are fed to the unit 2 together with the clock. On the other hand, in the unit 2, the timing of the shift register SRB 11 is taken and it is set by shifting the data serially delivered from SRA 10 to SRB 11 every one bit. By constituting the shift registers and two systems for transmission and reception as the transfer route, the information transfer between information processing units can be made.

9. 发明专利

JPS5525174A INITIAL PROGRAM LOAD START SYSTEM 失效
公开(公告)号：JPS5525174A
公开(公告)日：1980-02-22
申请号：JP9886978
申请日：1978-08-14
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： TOJIYAMA TAKASHI , USHIKI TATSUO , KANAZAWA NOBUHARU
IPC分类号： G06F1/00 , G06F9/445
摘要： PURPOSE:To start a program load circuit without reference to the suppression signal of an emergency control circuit by providing a circuit which releasing temporarily the suppression method of the emergency control circuit and then by sharing the emergency control circuit and initial program load circuit. CONSTITUTION:Emergency control circuit 7 is provided and the circuit which starts the initial program load for data processing is equipped with lock key SW1 for emergency control and non-lock key SW2 for initial program loading. When key SW2 is closed with circuit 7 in suppression action, program load display FF6 is reset to make NAND gate 4 ''0'' and circuit 7 is made to stay in suppression, thereby starting the microprogram. This actuation resets FF6 and makes the 4 ''1'', allowing the execution of the process of circuit 7. When circuit 7 is not in suppression, on the other hand, gate 4 is made ''1'' under the condition that key SW1 is off, and circuit 7 is shared as the program load circuit.

10. 发明专利

JPS5525868A DIAGNOSTIC SYSTEM FOR CONTROL MEMORY 失效
公开(公告)号：JPS5525868A
公开(公告)日：1980-02-23
申请号：JP9886678
申请日：1978-08-14
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： TOJIYAMA TAKASHI , SHINTANI HIROSHI , KANAZAWA NOBUHARU
IPC分类号： G06F12/16 , G06F11/10 , G06F11/22 , G11C29/00
摘要： PURPOSE:To evade a bad influence of an error control memory content upon other units, by invalidating the output of a control memory in diagnostic operation. CONSTITUTION:To diagnose unit 2 in a stop state by unit 1, the Q output of diagnostic mode FF12 is set to ''1'' via AND5 and the address of a control memory to be diagnosed is sent out via AND4, so that unit 2 will set the address to control memory address register 7. Then, information read out from control memory 8 is set to control memory latch register 9 and the Q output of FF12 changes into ''0''; and the microinstruction type assigning decoders is inhibited from operating to make all output ''0'' and control memory decoders 13 and 14 do not perform the control inside of the unit at all, so that parity check circuit 11 will check the control memory. By reading the parity check result by AND3, unit 1 completes the diagnosis of one word. Consequently, a bad influence upon other units can be avoided.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式