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1. 发明专利

JPH0480861A INTER-PROCESSOR PROGRAM CALLING SYSTEM 失效
公开(公告)号：JPH0480861A
公开(公告)日：1992-03-13
申请号：JP19513490
申请日：1990-07-24
申请人： FUJITSU LTD , FUJITSU NAGOYA TSUSHIN SYST KK
发明人： TANAKA YUTAKA , TERANISHI TOSHIBUMI
IPC分类号： G06F15/16 , G06F9/46 , G06F15/177
摘要： PURPOSE:To call out the programs among processors in a multiprocessor system by providing a processor processing portion storage means, a program start processing means, and a program reset processing means to each processor. CONSTITUTION:Each of processors 1-1 - 1-n is provided with a processor processing portion storage part 2, a program start processing part 3, and a program reset processing part 4. When a starting request of a 2nd program 6 is received from a 1st program 5 which is under execution of the processing with its own processor 1-1 or one of other processors P-2 - P-n, the part 3 inputs the identification information on the processors sharing the processing of the program 6 from the part 2 and starts the program 6 of the preceding processor. The part 4 sends the processing result to the program 5 after receiving the end information of processing and the processing result from the program 6.

2. 发明专利

JPH0677956A FINAL COMMUNICATION PATH BLOCK PREVENTING SYSTEM 失效
公开(公告)号：JPH0677956A
公开(公告)日：1994-03-18
申请号：JP22547992
申请日：1992-08-25
申请人： FUJITSU LTD
发明人： TANAKA YUTAKA
IPC分类号： H04L12/70 , H04L12/00
摘要： PURPOSE:To prevent a final speech path with a network managing center from being blocked by providing a routing control table for managing the states of all the speech paths to which respective exchanges are connected, and means for controlling so as not to block the final speech path at each exchange. CONSTITUTION:When a blocking instruction is received from the network managing center, a control part 11 checks it by retrieving a routing control table 10 whether the objective speech path of the blocking instruction is the final speech path or not. When the block object speech path is the final speech path, the control part 11 refuses the blocking instruction of the speech path. Thus, an exchange 1 is not isolated from the network managing center, and the final speech path to the network managing center can be prevented from being blocked.

3. 发明专利

JPS61175778A FORMATION OF FORM MODEL 失效
公开(公告)号：JPS61175778A
公开(公告)日：1986-08-07
申请号：JP1592385
申请日：1985-01-30
申请人： FUJITSU LTD
发明人： TANAKA YUTAKA , NAKAJIMA SHUICHI , OKAZAKI SADAAKI , AKATSUKA KOICHI , KATO AKIRA
IPC分类号： G06F17/50
摘要： PURPOSE:To attain the automatic production of an inside shell by forming an external form model as the gathering of faces and obtaining a face with the offset of desired thickness on a normal line which defines each face. CONSTITUTION:The position vector P2 of the face A is obtained from a position vector P1 which defines the face A, a normal line unit vector N1 and the thickness t1. Then ridgelines A' and B' are obtained from equations I and II of shell faces A' and B'. An equation III is obtained to obtain the equation IV of a face D'. Then the XYZ coordinates of apexes A', B' and D' are obtained as the intersecting points between the face D' (equation IV) and ridgelines A' and B' (equation III). Such operations are carried out with all faces to obtain the existing ridgelines and apexes.

4. 发明专利

JPS5828978B2 失效
公开(公告)号：JPS5828978B2
公开(公告)日：1983-06-20
申请号：JP15016277
申请日：1977-12-14
申请人： FUJITSU LTD
发明人： MORIDERA AKIO , YAJIMA SHOICHI , MASUDA TOORU , TANAKA YUTAKA
IPC分类号： H04N1/00 , H04L12/18 , H04L12/54 , H04L12/58 , H04L29/00

5. 发明专利

JPS57103561A INFORMATION COLLECTING SYSTEM DUTING EXECUTION OF PROGRAM 失效
公开(公告)号：JPS57103561A
公开(公告)日：1982-06-28
申请号：JP17956480
申请日：1980-12-18
申请人： FUJITSU LTD
发明人： TAKAHASHI HIDEO , TANAKA YUTAKA
IPC分类号： G06F11/34
摘要： PURPOSE:To minimize the change and the addition to a main program, by inserting only the calling instruction of the information collecting subroutine to an optional address requiring the collection of information for the main program and storing previously the information collecting parameter in a different table. CONSTITUTION:A subroutine 1-2 that collects the information is called out at an optional stage of a main program 1-1 to collect the variable data, the contents of a register, etc. In such system, only an instruction JSR is stored in an address (x) of the program 1-1 to read the routine 1-2. A table is provided to store the information collecting parameter along with a stack register 1-5 that stores a return address (y) of the program 1-1 when the routine 1-2 is called. Thus when the routine 1-2 is called out, the address (y) set to the register 1-5 is extracted. The index is carried out to a table 5 through the address (y) to extract the information collecting parameter. Then the collection is carried out for the information of a type that is designated by the above-mentioned parameter.

6. 发明专利

JPS5482101A INFORMATION TRANSFER SYSTEM 失效
公开(公告)号：JPS5482101A
公开(公告)日：1979-06-30
申请号：JP15016277
申请日：1977-12-14
申请人： FUJITSU LTD
发明人： MORIDERA AKIO , YAJIMA SHIYOUICHI , MASUDA TOORU , TANAKA YUTAKA
IPC分类号： H04N1/00 , H04L12/18 , H04L12/54 , H04L12/58 , H04L29/00
摘要： PURPOSE:To secure transmission the telegram of the same contents to an optional terminal in the necessary number of copies by having the transfer control at the center unit based on the copy number designation information given from the terminal in the storage communication system. CONSTITUTION:More than one unit of facsimile terminal unit T are installed, along with center unit 2', 2'' and 2'' which feature the function to receive and store the digital information transmitted from terminal T via communication circuit 7 as well as the function to transmit the storage information to terminal T via circuit 7. Center unit 2 contains the function to receive and decode the designation information concerning the necessary copy number of the telegram sent from outgoing terminal 1 or incoming terminal 3 as well as to control the transmission of the telegram to unit 3. Thus, the telegram can be transferred in the necessary number of copies to an optional incoming terminal unit among terminals T.

7. 发明专利

JPH0548654A LINE RESTART SYSTEM 失效
公开(公告)号：JPH0548654A
公开(公告)日：1993-02-26
申请号：JP20514591
申请日：1991-08-15
申请人： FUJITSU LTD
发明人： TANAKA YUTAKA
IPC分类号： H04L12/70
摘要： PURPOSE:To eliminate the need for assignment of a logic channel memory for line restart by the maintenance personnel with respect to the line restart system of a packet exchange. CONSTITUTION:A packet exchange 1 sets plural logic channels onto a physical line, sets a call corresponding to each logic channel for communication and allocates a logic channel memory 4 depending on a logic channel group number and a logic channel number into a line control memory 3 to identify each logic channel and uses a logic channel of a specific number of a logic channel group of a specific number prior to the communication with the packet form terminal equipment 2 to implement line restart processing. In this case, the line restart processing is not immediately at the reception of a line restart request packet or the line restart logic channel memory 5 is allocated at line registration and the line restart processing is implemented on the condition of the allocation of the logic channel memory 5 at the reception of the line restart request packet.

8. 发明专利

JPH03270443A SYSTEM FOR CONTROLLING MODEM WITH BUILT-IN BUFFER 失效
公开(公告)号：JPH03270443A
公开(公告)日：1991-12-02
申请号：JP6815890
申请日：1990-03-20
申请人： FUJITSU LTD , KOKUSAI DENSHIN DENWA CO LTD
发明人： TANAKA YUTAKA , NISHIYAMA YOICHI
IPC分类号： H04L29/02 , H04L12/00 , H04L29/10 , H04M11/00
摘要： PURPOSE:To prevent data from being abandoned when a line is cut in the case of executing data communication while using a MODEM with a built-in buffer by cutting the line after the lapse of fixed time when cutting the line. CONSTITUTION:A line cut control parts 3 executes control to cut the line after the fixed time (release guard timing) enough for transmitting data residual in the buffer at least from the reception of a line cut request for cutting the line to a MODEM 2 with the built-in buffer to the transmission of the final data. Namely, when a data exchange 1 detects the cause of the line cut, the transmitting data to announce such a state to a terminal side is transmitted and afterwards, the line is cut at the release guard timing. Thus, since the not-transmitted data residual in the internal buffer of the MODEM 2 with built-in buffer is transmitted to the terminal side during the release guard timing and there is no un-transmitted data when cutting the line, the data is not lost by cutting the line.

9. 发明专利

JPS6180463A Display processing system for curved surface 失效
标题翻译：弯曲表面显示处理系统
公开(公告)号：JPS6180463A
公开(公告)日：1986-04-24
申请号：JP20312384
申请日：1984-09-28
申请人： Fujitsu Ltd
发明人： AKATSUKA KOICHI , TANAKA YUTAKA , KATO AKIRA , NAKAJIMA SHUICHI , OKAZAKI SADAAKI
IPC分类号： G06F3/153 , G06F3/14 , G06T15/00
摘要： PURPOSE:To improve the processing efficiency for display of a curved surface and also to prevent the deviation of displayed pictures, by converting the 3- dimentional data to be displayed cubically into the 2-dimensional information and then converting the 2-dimensional information into the 3-dimensional data again after dividing an optional curved surface into basic polygons. CONSTITUTION:When the graphic processing (change of a cubic form, etc.) is carried out via a light pen 6 or a keyboard 5 of a display controller 4, a solid data handler 2 is started by a processing part 7. The handler 2 sends the solid model data SD taken out of a file 1 to a polygon dividing part 9 via a bus 8. The part 9 divides the data SD into surfaces and at first converts the 3-dimentional data into the 2-dimensional data via a 2-dimentional conversion part 10. In other words, the basic polygons obtained by dividing an optional curved surface are converted into the 2-dimensional parameter spaces without using the floating point arithmetic. These parameter spaces are converted again into the 3-dimensional data. Thus it is possible to improve the processing efficiency for display of a curved surface and also to prevent the deviation of displayed pictures.
摘要翻译：目的：为了提高显示曲面的处理效率，并且通过将三维数据立即转换为二维信息，然后将二维信息转换为二维信息，也可以防止显示图像的偏差将可选曲面分割成基本多边形后，再次进行三维数据处理。构成：当通过显示控制器4的光笔6或键盘5执行图形处理（立方体形式的更改等）时，由处理部分7启动实体数据处理程序2.处理程序2 经由总线8将从文件1取出的实体模型数据SD发送到多边形分割部9.部分9将数据SD划分成表面，并且首先通过2将3维数据转换成2维数据换句话说，通过将可选曲面分割而获得的基本多边形在不使用浮点运算的情况下被转换为二维参数空间。这些参数空间再次被转换为三维数据。因此，可以提高用于显示曲面的处理效率，并且还可以防止显示的图像的偏差。

10. 发明专利

JPH0265304A CURRENT MIRROR CIRCUIT 失效
公开(公告)号：JPH0265304A
公开(公告)日：1990-03-06
申请号：JP21803088
申请日：1988-08-30
申请人： FUJITSU LTD , FUJITSU VLSI LTD
发明人： TANAKA YUTAKA , FUNAKI TETSUJI , TAKIMOTO HISAICHI
IPC分类号： H03F3/343
摘要： PURPOSE:To reduce the dislocation of a mirror coefficient and to obtain a multi-output by keeping a connecting point between the respective bases of a first input transistor(Tr) and a second output Tr to a high potential rather than the potential of the connecting point between a basic input Tr and a basic output Tr, whose bases are commonly connected. CONSTITUTION:When an input current I1 is supplied from a constant current source 1, the current is divided into a base current IB4 of a third Tr Q4 and a collector current IC12 of a second input TrQ12. The base current IB4 is confluent with a collector current IC4 and goes to be an emitter current IE4. Then, the current is supplied to a second connecting point C. A diode D1 is is connected in a regular direction between the second connecting point C and a first connecting point B and regular direction potential drop is generated in the diode D1. Thus, Transistors Q11, Q21, and Q31 are operated with a base voltage which is lower than that of second Tr Q12, Q22 and Q32 only for the regular direction potential drop. Thus, the Tr Q11, Q21 and Q31 can be prevented to be saturated.

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