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1. 发明授权

US09793805B2 Charge pump current adjustment 有权
公开(公告)号：US09793805B2
公开(公告)日：2017-10-17
申请号：US14674385
申请日：2015-03-31
申请人： FUJITSU LIMITED
发明人： Nikola Nedovic
IPC分类号： H02M3/158 , H02M1/08 , H02M3/07 , H02M1/00
CPC分类号： H02M3/158 , H02M1/08 , H02M3/07 , H02M3/1588 , H02M2001/0003
摘要： A charge pump circuit may include an output node, a current source circuit, a current sink circuit, a first amplifier circuit, and a second amplifier circuit. The current source circuit may be configured to source current to the output node. The current sink circuit may be configured to sink current from the output node. The first amplifier circuit may be configured to adjust a first amount of current sourced by the current source circuit based on a voltage on the output node. The second amplifier circuit may be configured to adjust the first amount of current sourced by the current source circuit or a second amount of current sunk by the current sink circuit based on the voltage on the output node.

2. 发明授权

US09270289B2 Monolithic signal generation for injection locking 有权
标题翻译：单片信号发生注入锁定
公开(公告)号：US09270289B2
公开(公告)日：2016-02-23
申请号：US14179600
申请日：2014-02-13
申请人： FUJITSU LIMITED
发明人： William W. Walker , Nikola Nedovic
IPC分类号： H03K3/03 , H03L7/099 , H03B19/12 , H03B1/00 , H03B27/00
CPC分类号： H03L7/099 , H03B1/00 , H03B19/12 , H03B27/00 , H03K3/0315 , H03L7/0805 , H03L7/24
摘要： A system for signal generation may include a phase-locked-loop including a first oscillator. The system may also include a second oscillator. The first oscillator may be configured to generate a first signal based on a phase-locked-loop control signal generated by the phase-locked-loop. The second oscillator may be configured to generate a second signal based on the phase-locked-loop control signal such that a free-running frequency of the first signal is approximately equal to a free-running frequency of the second signal to obtain injection locking between the first oscillator and the second oscillator when energy from the first oscillator is coupled into the second oscillator.
摘要翻译：用于信号产生的系统可以包括包括第一振荡器的锁相环。系统还可以包括第二振荡器。第一振荡器可以被配置为基于由锁相环产生的锁相环控制信号来产生第一信号。第二振荡器可以被配置为基于锁相环控制信号产生第二信号，使得第一信号的自由运行频率近似等于第二信号的自由运行频率，以获得第二信号之间的注入锁定当来自第一振荡器的能量耦合到第二振荡器中时，第一振荡器和第二振荡器。

3. 发明授权

US09203381B2 Current mode logic latch 有权
标题翻译：电流模式逻辑锁存
公开(公告)号：US09203381B2
公开(公告)日：2015-12-01
申请号：US14268684
申请日：2014-05-02
申请人： Fujitsu Limited
发明人： Shuo-Chun Kao , Nikola Nedovic
IPC分类号： H03K3/356 , H03K3/0233
CPC分类号： H03K3/356 , H03K3/0233 , H03K3/356043
摘要： A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.
摘要翻译：电流模式逻辑锁存器可以包括采样级和保持级，保持级包括第一和第二级晶体管，第一和第二保持级电流源以及保持级开关。第一保持级晶体管可以在其漏极端子耦合到第一采样级晶体管的漏极端子。第二保持级晶体管可以在其漏极端子处耦合到第二采样级晶体管的漏极端子，其在其栅极端子处耦合到第一保持级晶体管的漏极端子，并且在其漏极端子耦合到栅极端子第一个保持晶体管。第一保持级电流源可以耦合到第一保持级晶体管的源极端子。第二保持级电流源可以耦合到第二保持级晶体管的源极端子。保持级开关可以耦合在第一保持级晶体管的源极端子和第二保持级晶体管的源极端子之间。

4. 发明授权

US09136828B2 Current mode logic latch 有权
公开(公告)号：US09136828B2
公开(公告)日：2015-09-15
申请号：US14268634
申请日：2014-05-02
申请人： Fujitsu Limited
发明人： Shuo-Chun Kao , Nikola Nedovic
IPC分类号： H03K3/356 , H03K3/0233
CPC分类号： H03K3/356 , H03K3/0233 , H03K3/356043
摘要： A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.

5. 发明授权

US10496921B2 Neural network mapping dictionary generation 有权
公开(公告)号：US10496921B2
公开(公告)日：2019-12-03
申请号：US15145664
申请日：2016-05-03
申请人： FUJITSU LIMITED
发明人： Xuan Tan , Nikola Nedovic
IPC分类号： G06N3/08 , G06N3/04 , H04L29/12 , G06N3/02
CPC分类号： G06N3/08 , G06N3/04 , H04L61/103 , G06N3/02
摘要： A method of generating mapping dictionaries for neural networks may be provided. A method may include receiving, at a current layer, encoded activation addresses from a previous layer and encoded weight addresses. The method may also include decoding the encoded activation addresses to generate decoded activation addresses, and decoding the encoded weight addresses to generate decoded weight addresses. Further, the method may include generating original activation addresses from the decoded activation addresses and the decoded weight addresses. Moreover, the method may include matching the original activation addresses to a mapping dictionary to generate encoded activation addresses for the current layer.

6. 发明授权

US09831861B2 Phase detector 有权
公开(公告)号：US09831861B2
公开(公告)日：2017-11-28
申请号：US14842591
申请日：2015-09-01
申请人： FUJITSU LIMITED
发明人： Nikola Nedovic
IPC分类号： H03L7/08 , H03K5/1534 , H03L7/081 , H03L7/091
CPC分类号： H03K5/1534 , H03L7/0814 , H03L7/0816 , H03L7/091
摘要： A phase detection circuit includes a first sample circuit, a second sample circuit, and a third sample circuit. The first sample circuit may be configured to sample a first signal based on a first phase of a second signal to generate a first sample of the first signal and to output the first sample. The second sample circuit may be configured to sample the first signal based on a second phase of the second signal to generate a second sample of the first signal and to output second sample. The third sample circuit coupled to the first sample circuit and to the second sample circuit. The third sample circuit may be configured to sample the first sample based on a change of the second sample to generate a third sample and to output the third sample.

7. 发明授权

US09153936B2 Power-efficient high-speed driver for a vertical-cavity surface-emitting laser 有权
标题翻译：用于垂直腔表面发射激光器的功率高效的高速驱动器
公开(公告)号：US09153936B2
公开(公告)日：2015-10-06
申请号：US13922793
申请日：2013-06-20
申请人： Fujitsu Limited
发明人： Tony Shuo-Chun Kao , Nikola Nedovic
IPC分类号： H01S5/042 , H01S5/026 , H01S5/062 , H01S5/183
CPC分类号： H01S5/0427 , H01S5/0261 , H01S5/042 , H01S5/06226 , H01S5/183
摘要： An optical transmitter is disclosed. In accordance with some embodiments of the present disclosure, an optical transmitter may comprise a vertical-cavity surface-emitting laser (VCSEL) and a VCSEL driver. The VCSEL driver may comprise an input stage configured to receive a voltage signal and a low-impedance output stage comprising an input coupled to the input stage and a low-impedance output coupled to the VCSEL and configured to provide a modulated output current to the VCSEL.
摘要翻译：公开了一种光发射机。根据本公开的一些实施例，光发射机可以包括垂直腔面发射激光器（VCSEL）和VCSEL驱动器。 VCSEL驱动器可以包括被配置为接收电压信号的输入级和包括耦合到输入级的输入和耦合到VCSEL的低阻抗输出的低阻抗输出级，并且被配置为向VCSEL提供调制输出电流。

8. 发明授权

US08971447B1 Variable delay of data signals 有权
标题翻译：数据信号的可变延迟
公开(公告)号：US08971447B1
公开(公告)日：2015-03-03
申请号：US14056069
申请日：2013-10-17
申请人： Fujitsu Limited
发明人： Shuo-Chun Kao , Nikola Nedovic
IPC分类号： H04K1/02 , H04L25/03
CPC分类号： H04L25/03343 , H04L25/0314
摘要： A data signal delay system may include a delay unit and a phase interpolation unit. The delay unit may include multiple delay elements that each have an element delay. The delay unit may be configured to generate multiple delay signals by delaying a data signal using the delay elements such that each of the delay signals has a different delay. The phase interpolation unit may be coupled to the delay unit and may include a mixer. The mixer may be configured to mix two of the delay signals based on mixing weights selected for the two delay signals to generate a final delayed data signal that is the data signal delayed by a final delay. The mixing weights may be selected based on the final delay.
摘要翻译：数据信号延迟系统可以包括延迟单元和相位插值单元。延迟单元可以包括多个具有元件延迟的延迟元件。延迟单元可以被配置为通过使用延迟元件延迟数据信号来产生多个延迟信号，使得每个延迟信号具有不同的延迟。相位插值单元可以耦合到延迟单元，并且可以包括混频器。混频器可以被配置为基于为两个延迟信号选择的混合权重混合两个延迟信号，以产生延迟最终延迟的数据信号的最终延迟数据信号。可以基于最终延迟来选择混合权重。

9. 发明授权

US08891704B2 Transimpedance amplifier with equalization 有权
标题翻译：具有均衡的互阻放大器
公开(公告)号：US08891704B2
公开(公告)日：2014-11-18
申请号：US13670219
申请日：2012-11-06
申请人： Fujitsu Limited
发明人： Scott McLeod , Nikola Nedovic
IPC分类号： H03D1/06
CPC分类号： H03F1/086 , H03F3/087 , H03F3/3022 , H03F3/45197 , H03F2203/30084 , H03F2203/30117 , H03F2203/30144 , H03F2203/45488 , H04L25/03878
摘要： In one embodiment, a method includes applying, by a transimpedance amplifier at a receiving end of a communication link, equalization to a signal carried by the communication link at the receiving end of the communication link.
摘要翻译：在一个实施例中，一种方法包括通过在通信链路的接收端处的跨阻抗放大器对通信链路的接收端处的通信链路承载的信号进行均衡。

10. 发明授权

US09658511B2 Optical ring resonator circuit 有权
公开(公告)号：US09658511B2
公开(公告)日：2017-05-23
申请号：US14671303
申请日：2015-03-27
申请人： FUJITSU LIMITED
发明人： Nikola Nedovic
IPC分类号： G02F1/035 , G02F1/225 , G02B6/12 , G02F1/01
CPC分类号： G02F1/2257 , G02B6/12004 , G02B2006/12142 , G02B2006/12159 , G02F1/0121
摘要： A method includes applying a voltage to an optical ring resonator circuit to adjust a resonance condition of a ring waveguide included in the optical ring resonator circuit. The method also includes detecting an amount of current generated by the optical ring resonator circuit and determining the resonance condition of the ring waveguide based on the detected amount of current.

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