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1. 发明申请

WO2009088897A3 INTEGRATED LOW LEAKAGE DIODE 审中-公开
公开(公告)号：WO2009088897A3
公开(公告)日：2009-07-16
申请号：PCT/US2008/088595
申请日：2008-12-31
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION , CAI, Jun
发明人： CAI, Jun
IPC分类号： H01L29/861
摘要： An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on.

2. 发明申请

WO2008112508A1 SHORT CHANNEL LV, MV, AND HV CMOS DEVICES 审中-公开
标题翻译： SHORT CHANNEL LV，MV和HV CMOS器件
公开(公告)号：WO2008112508A1
公开(公告)日：2008-09-18
申请号：PCT/US2008/056119
申请日：2008-03-07
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION , CAI, Jun
发明人： CAI, Jun
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L29/0653 , H01L29/1045 , H01L29/1083 , H01L29/1087 , H01L29/42368 , H01L29/665 , H01L29/66568 , H01L29/66575 , H01L29/6659 , H01L29/66659 , H01L29/7834
摘要： Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region.
摘要翻译：低压，中压和高电压CMOS器件具有与源极和漏极和栅极延伸但不超过栅极中间的源极和漏极相同的导电类型的上缓冲层，以及较低的主缓冲层与上缓冲层相反的导电类型从上缓冲层下延伸到栅极的中间，形成门下的两个体缓冲层的重叠。可以使用两个掩模层为NMOS和PMOS FET注入上缓冲层和下块体缓冲层。对于中压和高电压器件，上部缓冲层与较低的主缓冲层一起提供了一个复原区域。

3. 发明申请

WO2006033923A2 ENHANCED RESURF HVPMOS DEVICE WITH STACKED HETERO-DOPING RIM AND GRADUAL DRIFT REGION 审中-公开
标题翻译：具有堆叠异位移动和平滑移动区域的增强RESURF HVPMOS设备
公开(公告)号：WO2006033923A2
公开(公告)日：2006-03-30
申请号：PCT/US2005/032780
申请日：2005-09-14
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION , CAI, Jun , HARLEY-STEAD, Michael , HOLT, Jim, G.
发明人： CAI, Jun , HARLEY-STEAD, Michael , HOLT, Jim, G.
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/1045 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66659
摘要： An HV PMOS device formed on a substrate having an HV well of a first polarity type formed in an epitaxial layer of a second polarity type includes a pair of field oxide regions on the substrate and at least partially over the HV well. Insulated gates are formed on the substrate between the field oxide regions. Stacked hetero-doping rims are formed in the HV well and in self-alignment with outer edges of the gates. A buffer region of the first polarity type is formed in the HV well between and in self-alignment with inner edges of the gates. A drift region of the second polarity type is formed in the buffer region between and in self-alignment with inner edges of the gates. The drift region includes a region having a gradual dopant concentration change, and includes a drain region of the second polarity type.
摘要翻译：形成在具有形成在第二极性类型的外延层中的具有第一极性类型的HV阱的衬底上的HV PMOS器件包括在衬底上并且至少部分地在HV阱上的一对场氧化物区域。绝缘栅极形成在场氧化物区域之间的衬底上。堆叠的异质掺杂衬垫形成在HV阱中并与栅极的外边缘自对准。第一极性类型的缓冲区形成在HV阱中，并且与栅极的内边缘自对准。第二极性类型的漂移区域形成在缓冲区域中，并且与栅极的内边缘自对准。漂移区域包括具有逐渐掺杂浓度变化的区域，并且包括第二极性类型的漏极区域。

4. 发明申请

WO2007147102A2 HIGH VOLTAGE LDMOS 审中-公开
标题翻译：高压LDMOS
公开(公告)号：WO2007147102A2
公开(公告)日：2007-12-21
申请号：PCT/US2007/071310
申请日：2007-06-15
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION , CAI, Jun
发明人： CAI, Jun
IPC分类号： H01L27/12
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/41725 , H01L29/42356 , H01L29/4236 , H01L29/7825
摘要： A semiconductor device, such as a LDMOS device, comprising: a semiconductor substrate; a drain region in the semiconductor substrate; a source region in the semiconductor substrate laterally spaced from the drain region; and a drift region in the semiconductor substrate between the drain region and the source region. A gate is operatively coupled to the source region and is located offset from the drain region on a side of the source region opposite from the drain region. When the device is in an on state, current tends to flow deeper into the drift region to the offset gate, rather than near the device surface. The drift region preferably includes at least first and second stacked JFETs. The first and second stacked JFETs include first, second and third layers of a first conductivity type, a fourth layer intermediate the first and second layers including alternating pillars of the first conductivity type and of a second conductivity type extending between the source and drain regions; and a fifth layer intermediate the second and third layers, including alternating pillars of the first and second conductivity types extending between the source and drain regions.
摘要翻译：一种半导体器件，例如LDMOS器件，包括：半导体衬底; 半导体衬底中的漏区; 所述半导体衬底中的源极区域与所述漏极区域横向间隔开; 以及在漏极区域和源极区域之间的半导体衬底中的漂移区域。栅极可操作地耦合到源极区域并且位于与漏极区域相对的源极区域侧上的漏极区域偏移。当器件处于导通状态时，电流趋向于更深地流入偏移栅极的漂移区域，而不是靠近器件表面。漂移区优选地包括至少第一和第二堆叠JFET。第一和第二堆叠JFET包括第一导电类型的第一，第二和第三层，第一和第二层中间的第四层，包括第一导电类型的交替柱和在源极和漏极区之间延伸的第二导电类型; 以及第二层和第三层之间的第五层，包括在源区和漏区之间延伸的第一和第二导电类型的交替柱。

5. 发明申请

WO2006020064A2 ASYMMETRIC HETERO-DOPED HIGH-VOLTAGE MOSFET (AH2MOS) 审中-公开
标题翻译：不对称异质高压MOSFET（AH2MOS）
公开(公告)号：WO2006020064A2
公开(公告)日：2006-02-23
申请号：PCT/US2005/025212
申请日：2005-07-14
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION , CAI, Jun , HARLEY-STEAD, Michael , HOLT, Jim, G.
发明人： CAI, Jun , HARLEY-STEAD, Michael , HOLT, Jim, G.
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L29/0847 , H01L21/823425 , H01L21/823481 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/665 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： An asymmetric heterodoped metal oxide (AH 2 MOS) semiconductor device includes a substrate and an insulated gate on the top of the substrate disposed between a source region and a drain region. On one side of the gate, heterodoped tub and source regions are formed. The tub region has dopants of a second polarity. A source region is disposed inside each tub region and has dopants of a first polarity opposite to the second polarity. On the other side of the gate, heterodoped buffer and drift regions are formed. The buffer regions comprise dopants of the second polarity. The drift regions are disposed inside the buffer regions and are doped with dopants of the first polarity. A drain n+ tap region is disposed in the drift region.
摘要翻译：不对称异源金属氧化物（AH

6. 发明申请

WO2009132162A2 INTEGRATED LOW LEAKAGE SCHOTTKY DIODE 审中-公开
标题翻译：集成低漏电肖特基二极管
公开(公告)号：WO2009132162A2
公开(公告)日：2009-10-29
申请号：PCT/US2009/041480
申请日：2009-04-23
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION , CAI, Jun
发明人： CAI, Jun
IPC分类号： H01L29/872
CPC分类号： H01L29/861 , H01L29/0626 , H01L29/10 , H01L29/402 , H01L29/47 , H01L29/66143 , H01L29/872
摘要： An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N- layer over a P- layer which also forms the drift region that ends at the diode's cathode in one embodiment of the present invention. The N- and P- layers have an upward concave shape under the gate. The gate electrode and the Schottky metal are connected to the diode's anode. A P- layer lies between the RESURF structure and an NISO region which has an electrical connection to the anode. A P+ layer under the Schottky metal is in contact with the P- layer through a P well.
摘要翻译：集成的低泄漏肖特基二极管在MOS栅极的一侧具有肖特基势垒结，其栅极的相对侧上具有漂移区的一端。在肖特基金属之下和栅极氧化物是在本发明的一个实施方案中，P-层上的N层的RESURF结构，其也形成在二极管阴极处结束的漂移区。 N和P-层在栅极下方具有向上的凹形。栅电极和肖特基金属连接到二极管的阳极。 P层位于RESURF结构和与阳极电连接的NISO区域之间。肖特基金属下的P +层通过P阱与P-层接触。

7. 发明申请

WO2008067269A1 INTEGRATED LATCH-UP FREE INSULATED GATE BIPOLAR TRANSISTOR 审中-公开
标题翻译：集成式无锁绝缘栅双极晶体管
公开(公告)号：WO2008067269A1
公开(公告)日：2008-06-05
申请号：PCT/US2007/085561
申请日：2007-11-27
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION , CAI, Jun
发明人： CAI, Jun
IPC分类号： H01L29/70 , H01L29/73
CPC分类号： H01L29/7394 , H01L29/0634 , H01L29/0834 , H01L29/0847
摘要： A lateral Insulated Gate Bipolar Transistor (LIGBT) includes a semiconductor substrate and an anode region in the semiconductor substrate. A cathode region of a first conductivity type in the substrate is laterally spaced from the anode region, and a cathode region of a second conductivity type in the substrate is located proximate to and on a side of the cathode region of the first conductivity type opposite from the anode region. A drift region in the semiconductor substrate extends between the anode region and the cathode region of the first conductivity type. An insulated gate is operatively coupled to the cathode region of the first conductivity type and is located on a side of the cathode region of the first conductivity type opposite from the anode region. An insulating spacer overlies the cathode region of the second conductivity type. The lateral dimensions of the insulating spacer and the cathode region of the second conductivity type are substantially equal and substantially smaller than the lateral dimension of the cathode region of the first conductivity type.
摘要翻译：横向绝缘栅双极晶体管（LIGBT）包括半导体衬底和半导体衬底中的阳极区域。衬底中的第一导电类型的阴极区域与阳极区域横向间隔开，并且衬底中第二导电类型的阴极区域位于与第一导电类型相反的阴极区域附近和侧面阳极区域。半导体衬底中的漂移区域在第一导电类型的阳极区域和阴极区域之间延伸。绝缘栅极可操作地耦合到第一导电类型的阴极区域，并且位于与阳极区域相反的第一导电类型的阴极区域的一侧。绝缘间隔物覆盖第二导电类型的阴极区域。绝缘间隔物和第二导电类型的阴极区域的横向尺寸基本相等并且基本上小于第一导电类型的阴极区域的横向尺寸。

8. 发明申请

WO2007118060A3 SELF-ALIGNED COMPLEMENTARY LDMOS 审中-公开
公开(公告)号：WO2007118060A3
公开(公告)日：2007-10-18
申请号：PCT/US2007/065822
申请日：2007-04-03
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION , CAI, Jun
发明人： CAI, Jun
IPC分类号： H01L29/76
摘要： The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-slate. A version of the device includes a low threshold voltage version with a thin gate oxide on the source side of the device and a high threshold voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA, to reduce the device size and to reduce the device leakage.

9. 发明申请

WO2010090980A3 HIGH SPEED, LOW POWER CONSUMPTION, ISOLATED ANALOG CMOS UNIT 审中-公开
公开(公告)号：WO2010090980A3
公开(公告)日：2010-08-12
申请号：PCT/US2010/022812
申请日：2010-02-02
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION , CAI, Jun
发明人： CAI, Jun
IPC分类号： H01L29/78 , H01L21/336
摘要： A semiconductor device (100) has N-well regions (18) holding PMOS devices (110, 112) and P-type regions (14) holding NMOS devices (114, 116). Devices (110) and (114) have high thresholds and devices (112) and (116) have low thresholds. The PMOS devices are junction isolated from the substrate (10) by the N-well (18) and the NMOS devices are isolated from the substrate by the N- type layer (13). Field oxide regions (20) laterally isolate the PMOS from the NMOS devices. The high threshold CMOS devices (110, 114) connect the low threshold CMOS devices to opposite rails Vdd and Vss. A control terminal (121) turns the high threshold devices on to let the low threshold devices switch rapidly. In stand-by mode, the high threshold devices are off and there is very low leakage current.

10. 发明申请

WO2009117279A2 LDMOS DEVICES WITH IMPROVED ARCHITECTURES 审中-公开
标题翻译：具有改进架构的LDMOS器件
公开(公告)号：WO2009117279A2
公开(公告)日：2009-09-24
申请号：PCT/US2009/036632
申请日：2009-03-10
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION , CAI, Jun
发明人： CAI, Jun
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L27/088 , H01L21/26586 , H01L21/823412 , H01L21/823462 , H01L29/0878 , H01L29/1083 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66689 , H01L29/7816
摘要： An LDMOS device includes a substrate of a first conductivity type, an epitaxial layer on the substrate, a buried well of a second conductivity type opposite to the first conductivity type in a lower portion of the epitaxial layer, the epitaxial layer being of the first conductivity type below the buried layer. The device further includes a field oxide located between a drain and both a gate on a gate oxide and a source with a saddle shaped vertical doping gradient of the second conductivity type in the epitaxial layer above the buried well such that the dopant concentration in the epitaxial layer above the buried well and below a central portion of the field oxide is lower than the dopant concentration at the edges of the field oxide nearest the drain and nearest the gate.
摘要翻译：一种LDMOS器件包括：第一导电类型的衬底，在衬底上的外延层，在外延层的下部中的与第一导电类型相反的第二导电类型的掩埋阱，该外延层在埋层下方为第一导电类型。该器件还包括位于栅极氧化物上的漏极和栅极之间的场氧化物和位于掩埋阱上方的外延层中的具有第二导电类型的鞍形垂直掺杂梯度的源极，使得外延层中的掺杂剂浓度隐埋阱上方和场氧化物中心部分下方的层的掺杂浓度低于最靠近漏极且离栅极最近的场氧化物边缘处的掺杂浓度。

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