专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP1134665A3 UART with compressed user accessible interrupt codes 有权
标题翻译： UART与压缩和由用户访问中断代码
公开(公告)号：EP1134665A3
公开(公告)日：2004-01-14
申请号：EP00308831.7
申请日：2000-10-06
申请人： Exar Corporation
发明人： Wegner, Glenn
IPC分类号： G06F13/38 , G06F13/24
CPC分类号： G06F13/385
摘要： An improved UART (10) which has a number of channels (12), with each channel (12) having a set of channel configuration registers. Each channel configuration register includes an interrupt source register. The interrupt source register has a multi-bit interrupt source code which is used to indicate the source of the interrupt. This code is chosen to be compatible with prior UART devices. The device also includes a bus interface (26), and a plurality of device configuration registers (30) accessible through the bus interface by a user. One of the device configuration registers is an interrupt register (32) which provides a user accessible code to indicate the interrupt source. The code used for the interrupt source is a compressed version of the multiple bit code used in the channel configuration interrupt source register (38, 40). This compression allows more channels to be represented in a single register, while also conveying the interrupt source information quickly to the user. Since the device interrupt register (32) in the configuration registers is for access by the user, rather than internal access by UART drivers, there is no need for compatability with the prior UART drivers.

2. 发明公开

EP1134666A2 Uart automatic half-duplex direction control with programmable delay 有权
标题翻译：在Halbduplex-Richtung mit程序员Verzögerung中自动启动UART
公开(公告)号：EP1134666A2
公开(公告)日：2001-09-19
申请号：EP00308832.5
申请日：2000-10-06
申请人： Exar Corporation
发明人： Lo, Sun Man , Wegner, Glenn
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： A UART (10) with a FIFO buffer (14) is provided. A circuit (46) detects a last word transmitted from the FIFO buffer. A transmitter empty circuit generates a transmitter empty signal (RTS) when the last word transmitted from the FIFO buffer is detected. A delay circuit delays generation of the RTS signal for a programmable time delay. The time delay via a register (50) that is programmable by the user. The invention thus provides the programmable delay on the same chip as the UART (10).
摘要翻译：提供具有FIFO缓冲器（14）的UART（10）。电路（46）检测从FIFO缓冲器发送的最后一个字。当检测到从FIFO缓冲器发送的最后一个字时，发送器空电路产生发送器空信号（RTS）。延迟电路延迟RTS信号的产生用于可编程时间延迟。经由可由用户编程的寄存器（50）的时间延迟。因此，本发明在与UART（10）相同的芯片上提供可编程延迟。

3. 发明公开

EP1134665A2 UART with compressed user accessible interrupt codes 有权
标题翻译：。。。en en en en en en。。。。。。。。。。。。。。。。。。。。。
公开(公告)号：EP1134665A2
公开(公告)日：2001-09-19
申请号：EP00308831.7
申请日：2000-10-06
申请人： Exar Corporation
发明人： Wegner, Glenn
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： An improved UART (10) which has a number of channels (12), with each channel (12) having a set of channel configuration registers. Each channel configuration register includes an interrupt source register. The interrupt source register has a multi-bit interrupt source code which is used to indicate the source of the interrupt. This code is chosen to be compatible with prior UART devices. The device also includes a bus interface (26), and a plurality of device configuration registers (30) accessible through the bus interface by a user. One of the device configuration registers is an interrupt register (32) which provides a user accessible code to indicate the interrupt source. The code used for the interrupt source is a compressed version of the multiple bit code used in the channel configuration interrupt source register (38, 40). This compression allows more channels to be represented in a single register, while also conveying the interrupt source information quickly to the user. Since the device interrupt register (32) in the configuration registers is for access by the user, rather than internal access by UART drivers, there is no need for compatability with the prior UART drivers.
摘要翻译：一种改进的UART（10），其具有多个信道（12），每个信道（12）具有一组信道配置寄存器。每个通道配置寄存器包括一个中断源寄存器。中断源寄存器有一个多位中断源代码，用于指示中断源。该代码被选择为与以前的UART器件兼容。该设备还包括总线接口（26）以及由用户通过总线接口访问的多个设备配置寄存器（30）。设备配置寄存器之一是中断寄存器（32），其提供用户可访问代码来指示中断源。用于中断源的代码是通道配置中断源寄存器（38,40）中使用的多位代码的压缩版本。该压缩允许在单个寄存器中表示更多的通道，同时还向用户快速传递中断源信息。由于配置寄存器中的器件中断寄存器（32）用于用户访问，而不是UART驱动程序的内部访问，因此不需要与以前的UART驱动程序兼容。

4. 发明授权

EP1134665B1 UART with compressed user accessible interrupt codes 有权
标题翻译： UART与压缩和由用户访问中断代码
公开(公告)号：EP1134665B1
公开(公告)日：2008-01-02
申请号：EP00308831.7
申请日：2000-10-06
申请人： Exar Corporation
发明人： Wegner, Glenn
IPC分类号： G06F13/38 , G06F13/24
CPC分类号： G06F13/385

5. 发明授权

EP1134666B1 Uart automatic half-duplex direction control with programmable delay 有权
标题翻译：与可编程延迟半双工方向自动UART控制
公开(公告)号：EP1134666B1
公开(公告)日：2007-01-03
申请号：EP00308832.5
申请日：2000-10-06
申请人： Exar Corporation
发明人： Lo, Sun Man , Wegner, Glenn
IPC分类号： G06F13/38
CPC分类号： G06F13/385

6. 发明公开

EP1134667A3 Uart clock wake-up sequence 审中-公开
标题翻译： Uart时钟唤醒序列
公开(公告)号：EP1134667A3
公开(公告)日：2004-03-10
申请号：EP00308833.3
申请日：2000-10-06
申请人： Exar Corporation
发明人： Lo, Sun Man , Wegner, Glenn
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： A UART (10) with a clock oscillator (32) that has a sleep mode. A counter is connected to the output of the clock oscillator. When the clock oscillator (32) is awakened, the counter (38) counts up to a specified count. Upon reaching the specified count, the output of the counter (38) is enabled, which is connected to an interrupt line (40) for generating an interrupt. In one embodiment, the IC need not be a UART, and no interrupt code (or a default code of all zeros or other default) is provided for the interrupt, thus eliminating the need for an additional interrupt register or additional room in existing interrupt registers. The user, such as a CPU, upon receiving the interrupt will look for an interrupt code. The absence of the interrupt code, combined with the user's knowledge that the integrated circuit was previously asleep, allows the user to determine that the interrupt indicates a clock wake-up.
摘要翻译：一种具有时钟振荡器（32）的UART（10），具有睡眠模式。计数器连接到时钟振荡器的输出。当时钟振荡器（32）唤醒时，计数器（38）计数达到指定的计数值。在达到指定计数时，计数器（38）的输出被启用，其连接到用于产生中断的中断线（40）。在一个实施例中，IC不需要是UART，并且不为中断提供中断代码（或全零或其他缺省的默认代码），从而不需要在现有中断寄存器中增加中断寄存器或额外空间。用户（如CPU）在接收到中断时将查找中断代码。缺少中断代码，加上用户已知集成电路先前处于睡眠状态，使用户可以确定中断指示时钟被唤醒。

7. 发明公开

EP1134666A3 Uart automatic half-duplex direction control with programmable delay 有权
标题翻译：与可编程延迟半双工方向自动UART控制
公开(公告)号：EP1134666A3
公开(公告)日：2004-02-25
申请号：EP00308832.5
申请日：2000-10-06
申请人： Exar Corporation
发明人： Lo, Sun Man , Wegner, Glenn
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： A UART (10) with a FIFO buffer (14) is provided. A circuit (46) detects a last word transmitted from the FIFO buffer. A transmitter empty circuit generates a transmitter empty signal (RTS) when the last word transmitted from the FIFO buffer is detected. A delay circuit delays generation of the RTS signal for a programmable time delay. The time delay via a register (50) that is programmable by the user. The invention thus provides the programmable delay on the same chip as the UART (10).

8. 发明公开

EP1134667A2 Uart clock wake-up sequence 审中-公开
标题翻译： UART-Taktaufwecksequenz
公开(公告)号：EP1134667A2
公开(公告)日：2001-09-19
申请号：EP00308833.3
申请日：2000-10-06
申请人： Exar Corporation
发明人： Lo, Sun Man , Wegner, Glenn
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： A UART (10) with a clock oscillator (32) that has a sleep mode. A counter is connected to the output of the clock oscillator. When the clock oscillator (32) is awakened, the counter (38) counts up to a specified count. Upon reaching the specified count, the output of the counter (38) is enabled, which is connected to an interrupt line (40) for generating an interrupt. In one embodiment, the IC need not be a UART, and no interrupt code (or a default code of all zeros or other default) is provided for the interrupt, thus eliminating the need for an additional interrupt register or additional room in existing interrupt registers. The user, such as a CPU, upon receiving the interrupt will look for an interrupt code. The absence of the interrupt code, combined with the user's knowledge that the integrated circuit was previously asleep, allows the user to determine that the interrupt indicates a clock wake-up.
摘要翻译：具有休眠模式的具有时钟振荡器（32）的UART（10）。计数器连接到时钟振荡器的输出。当时钟振荡器（32）被唤醒时，计数器（38）计数到指定的计数。在达到指定计数时，计数器（38）的输出被使能，该输出连接到用于产生中断的中断线（40）。在一个实施例中，IC不需要是UART，并且不为中断提供中断代码（或全部为零或其他默认值的默认代码），因此无需额外的中断寄存器或现有中断寄存器中的额外空间。用户（如CPU）在接收到中断时将寻找中断代码。中断代码的不存在，结合用户先前已经睡觉的知识，允许用户确定中断指示时钟唤醒。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式