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1. 发明申请

US20110276732A1 PROGRAMMABLE QUEUE STRUCTURES FOR MULTIPROCESSORS 有权
标题翻译：可编程的多用户队列结构
公开(公告)号：US20110276732A1
公开(公告)日：2011-11-10
申请号：US12777084
申请日：2010-05-10
申请人： Evan Gewirtz , Robert Hathaway , Stephan Meier
发明人： Evan Gewirtz , Robert Hathaway , Stephan Meier
IPC分类号： G06F5/16
CPC分类号： G06F9/544 , G06F9/52
摘要： A command is received from a first agent via a first predetermined memory-mapped register, the first agent being one of multiple agents representing software processes, each being executed by one of processor cores of a network processor in a network element. A first queue associated with the command is identified based on the first predetermined memory-mapped register. A pointer is atomically read from a first hardware-based queue state register associated with the first queue. Data is atomically accessed at a memory location of the memory based on the pointer. The pointer stored in the first hardware-based queue state register is atomically updated, including incrementing the pointer of the first hardware-based queue state register, reading a queue size of the queue from a first hardware-based configuration register associated with the first queue, and wrapping around the pointer if the pointer reaches an end of the first queue based on the queue size.
摘要翻译：经由第一预定存储器映射寄存器从第一代理接收到命令，第一代理是表示软件进程的多个代理之一，每个由代理网络元件中的网络处理器的处理器核心之一执行。基于第一预定存储器映射寄存器来识别与命令相关联的第一队列。从与第一队列相关联的第一基于硬件的队列状态寄存器中原子地读取指针。基于指针，数据在存储器的存储器位置被原子访问。存储在第一基于硬件的队列状态寄存器中的指针被原子地更新，包括增加第一基于硬件的队列状态寄存器的指针，从与第一队列相关联的第一基于硬件的配置寄存器读取队列的队列大小并且如果指针基于队列大小到达第一队列的末尾，则环绕指针。

2. 发明授权

US08656139B2 Digital processor for processing long and short pointers and converting each between a common format 有权
标题翻译：用于处理长和短指针的数字处理器，并在通用格式之间进行转换
公开(公告)号：US08656139B2
公开(公告)日：2014-02-18
申请号：US13045919
申请日：2011-03-11
申请人： Stephan Meier , John G. Favor , Evan Gewirtz , Robert Hathaway , Eric Trehus
发明人： Stephan Meier , John G. Favor , Evan Gewirtz , Robert Hathaway , Eric Trehus
IPC分类号： G06F12/00
CPC分类号： G06F9/30043 , G06F9/342
摘要： A digital processor stores pointers of different sizes in memory. The processor, specifically, executes instructions to store a long or short pointer. Long pointers reference any address in the memory's logical address space, while short pointers merely reference any address in a subset of that space. However, short pointers are smaller in size as stored in memory than long pointers. Long pointers thus support relatively large address range capabilities, while short pointers use less memory. The processor also executes instructions to load a long or short pointer into the register file, and does so in a way that does not require the processor to distinguish between the different pointers when executing other instructions. Specifically, the processor converts long and short pointers into a common format for loading into the register file, and converts pointers in the common format back into long or short pointers for storing in the memory.
摘要翻译：数字处理器将不同大小的指针存储在存储器中。处理器具体地执行指令来存储长或短指针。长指针引用存储器逻辑地址空间中的任何地址，而短指针仅引用该空间子集中的任何地址。然而，短指针的大小比存储在内存中的长度小于长指针。因此，长指针支持相对较大的地址范围功能，而短指针使用较少的内存。处理器还执行将长指针或短指针加载到寄存器文件中的指令，并以不需要处理器在执行其他指令时区分不同指针的方式执行指令。具体来说，处理器将长指针和短指针转换为用于加载到寄存器文件中的通用格式，并将通用格式的指针转换为长或短指针以存储在存储器中。

3. 发明申请

US20120233414A1 SHORT POINTERS 有权
标题翻译：短指针
公开(公告)号：US20120233414A1
公开(公告)日：2012-09-13
申请号：US13045919
申请日：2011-03-11
申请人： Stephan Meier , John G. Favor , Evan Gewirtz , Robert Hathaway , Eric Trehus
发明人： Stephan Meier , John G. Favor , Evan Gewirtz , Robert Hathaway , Eric Trehus
IPC分类号： G06F12/00
CPC分类号： G06F9/30043 , G06F9/342
摘要： A digital processor stores pointers of different sizes in memory. The processor, specifically, executes instructions to store a long or short pointer. Long pointers reference any address in the memory's logical address space, while short pointers merely reference any address in a subset of that space. However, short pointers are smaller in size as stored in memory than long pointers. Long pointers thus support relatively large address range capabilities, while short pointers use less memory. The processor also executes instructions to load a long or short pointer into the register file, and does so in a way that does not require the processor to distinguish between the different pointers when executing other instructions. Specifically, the processor converts long and short pointers into a common format for loading into the register file, and converts pointers in the common format back into long or short pointers for storing in the memory.
摘要翻译：数字处理器将不同大小的指针存储在存储器中。处理器具体地执行指令来存储长或短指针。长指针引用存储器逻辑地址空间中的任何地址，而短指针仅引用该空间子集中的任何地址。然而，短指针的大小比存储在内存中的长度小于长指针。因此，长指针支持相对较大的地址范围功能，而短指针使用较少的内存。处理器还执行将长指针或短指针加载到寄存器文件中的指令，并以不需要处理器在执行其他指令时区分不同指针的方式执行指令。具体来说，处理器将长指针和短指针转换为用于加载到寄存器文件中的通用格式，并将通用格式的指针转换为长或短指针以存储在存储器中。

4. 发明申请

US20120173841A1 Explicitly Regioned Memory Organization in a Network Element 失效
标题翻译：网络元素中明确区域内存组织
公开(公告)号：US20120173841A1
公开(公告)日：2012-07-05
申请号：US12983130
申请日：2010-12-31
申请人： Stephan Meier , Robert Hathaway , Evan Gewirtz , Brian Alleyne , Edward Ho
发明人： Stephan Meier , Robert Hathaway , Evan Gewirtz , Brian Alleyne , Edward Ho
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F2213/0038 , Y02D10/13
摘要： A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory. The physical memory address includes a network routing information portion that includes information to route the physical memory address to the target instance, and includes an address payload portion that includes information to identify the physical address space identified by the subtarget and the physical memory address offset.
摘要翻译：包含多种存储器类型和存储器大小的网络元件将逻辑存储器地址转换为物理存储器地址。接收到具有逻辑存储器地址的数据结构的存储器访问请求，逻辑存储器地址包括标识映射到一个或多个存储器的区域的区域标识符，并且与其值基于处理的一个或多个区域属性的集合相关联由软件程序员提供的要求和网元的可用存储器。网元访问对应于区域标识符的区域映射表条目，并且使用与该区域相关联的区域属性来确定该请求的访问目标，确定访问目标内的物理内存地址偏移量，并且生成物理内存地址。访问目标包括目标类别的存储器，存储器类内的实例以及存储器类内的实例的特定物理地址空间。物理存储器地址包括网络路由信息部分，其包括用于将物理存储器地址路由到目标实例的信息，并且包括地址有效载荷部分，其包括用于识别由子目标识别的物理地址空间的信息和物理存储器地址偏移。

5. 发明授权

US08402248B2 Explicitly regioned memory organization in a network element 失效
标题翻译：在网络元素中明确区分的内存组织
公开(公告)号：US08402248B2
公开(公告)日：2013-03-19
申请号：US12983130
申请日：2010-12-31
申请人： Stephan Meier , Robert Hathaway , Evan Gewirtz , Brian Alleyne , Edward Ho
发明人： Stephan Meier , Robert Hathaway , Evan Gewirtz , Brian Alleyne , Edward Ho
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F2213/0038 , Y02D10/13
摘要： A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory. The physical memory address includes a network routing information portion that includes information to route the physical memory address to the target instance, and includes an address payload portion that includes information to identify the physical address space identified by the subtarget and the physical memory address offset.
摘要翻译：包含多种存储器类型和存储器大小的网络元件将逻辑存储器地址转换为物理存储器地址。接收到具有逻辑存储器地址的数据结构的存储器访问请求，逻辑存储器地址包括标识映射到一个或多个存储器的区域的区域标识符，并且与其值基于处理的一个或多个区域属性的集合相关联由软件程序员提供的要求和网元的可用存储器。网元访问对应于区域标识符的区域映射表条目，并且使用与该区域相关联的区域属性来确定该请求的访问目标，确定访问目标内的物理内存地址偏移量，并且生成物理内存地址。访问目标包括目标类别的存储器，存储器类内的实例以及存储器类内的实例的特定物理地址空间。物理存储器地址包括网络路由信息部分，其包括用于将物理存储器地址路由到目标实例的信息，并且包括地址有效载荷部分，其包括用于识别由子目标识别的物理地址空间的信息和物理存储器地址偏移。

6. 发明申请

US20110276784A1 HIERARCHICAL MULTITHREADED PROCESSING 审中-公开
标题翻译：分层多元处理
公开(公告)号：US20110276784A1
公开(公告)日：2011-11-10
申请号：US12777087
申请日：2010-05-10
申请人： Evan Gewirtz , Robert Hathaway , Stephan Meier , Edward Ho
发明人： Evan Gewirtz , Robert Hathaway , Stephan Meier , Edward Ho
IPC分类号： G06F9/312 , G06F9/30
CPC分类号： G06F9/3851 , G06F9/3802
摘要： In one embodiment, a current candidate thread is selected from each of multiple first groups of threads using a low granularity selection scheme, where each of the first groups includes multiple threads and first groups are mutually exclusive. A second group of threads is formed comprising the current candidate thread selected from each of the first groups of threads. A current winning thread is selected from the second group of threads using a high granularity selection scheme. An instruction is fetched from a memory based on a fetch address for a next instruction of the current winning thread. The instruction is then dispatched to one of the execution units for execution, whereby execution stalls of the execution units are reduced by fetching instructions based on the low granularity and high granularity selection schemes.
摘要翻译：在一个实施例中，使用低粒度选择方案从多个第一组线程中选择当前候选线程，其中每个第一组包括多个线程，并且第一组是互斥的。形成第二组线程，包括从第一组线程中选择的当前候选线程。使用高粒度选择方案从第二组线程中选择当前获胜线程。基于当前获胜线程的下一条指令的获取地址从存储器中取出指令。然后将指令分派到一个执行单元进行执行，由此通过基于低粒度和高粒度选择方案获取指令来减少执行单元的执行停顿。

7. 发明授权

US08051227B1 Programmable queue structures for multiprocessors 有权
标题翻译：多处理器的可编程队列结构
公开(公告)号：US08051227B1
公开(公告)日：2011-11-01
申请号：US12777084
申请日：2010-05-10
申请人： Evan Gewirtz , Robert Hathaway , Stephan Meier
发明人： Evan Gewirtz , Robert Hathaway , Stephan Meier
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F9/544 , G06F9/52
摘要： A command is received from a first agent via a first predetermined memory-mapped register, the first agent being one of multiple agents representing software processes, each being executed by one of processor cores of a network processor in a network element. A first queue associated with the command is identified based on the first predetermined memory-mapped register. A pointer is atomically read from a first hardware-based queue state register associated with the first queue. Data is atomically accessed at a memory location of the memory based on the pointer. The pointer stored in the first hardware-based queue state register is atomically updated, including incrementing the pointer of the first hardware-based queue state register, reading a queue size of the queue from a first hardware-based configuration register associated with the first queue, and wrapping around the pointer if the pointer reaches an end of the first queue based on the queue size.
摘要翻译：经由第一预定存储器映射寄存器从第一代理接收到命令，第一代理是表示软件进程的多个代理之一，每个由代理网络元件中的网络处理器的处理器核心之一执行。基于第一预定存储器映射寄存器来识别与命令相关联的第一队列。从与第一队列相关联的第一基于硬件的队列状态寄存器中原子地读取指针。基于指针，数据在存储器的存储器位置被原子访问。存储在第一基于硬件的队列状态寄存器中的指针被原子地更新，包括增加第一基于硬件的队列状态寄存器的指针，从与第一队列相关联的第一基于硬件的配置寄存器读取队列的队列大小并且如果指针基于队列大小到达第一队列的末尾，则环绕指针。

8. 发明授权

US08914581B2 Method and apparatus for accessing cache memory 有权
标题翻译：用于访问高速缓冲存储器的方法和装置
公开(公告)号：US08914581B2
公开(公告)日：2014-12-16
申请号：US12784276
申请日：2010-05-20
申请人： Robert Hathaway , Evan Gewirtz
发明人： Robert Hathaway , Evan Gewirtz
IPC分类号： G06F12/12 , G06F12/08
CPC分类号： G06F12/0888 , G06F12/12
摘要： A request for reading data from a memory location of a main memory is received, the memory location being identified by a physical memory address. In response to the request, a cache memory is accessed based on the physical memory address to determine whether the cache memory contains the data being requested. The data associated with the request is returned from the cache memory without accessing the memory location if there is a cache hit. The data associated is returned from the main memory if there is a cache miss. In response to the cache miss, it is determined whether there have been a number of accesses within a predetermined period of time. A cache entry is allocated from the cache memory to cache the data if there have been a predetermined number of accesses within the predetermined period of time.
摘要翻译：接收到从主存储器的存储器位置读取数据的请求，存储器位置由物理存储器地址标识。响应于该请求，基于物理存储器地址访问高速缓存存储器，以确定高速缓冲存储器是否包含正被请求的数据。如果存在高速缓存命中，与请求相关联的数据从高速缓冲存储器返回，而不访问存储器位置。如果存在高速缓存未命中，则从主存储器返回相关的数据。响应于高速缓存未命中，确定在预定时间段内是否存在多个访问。如果在预定时间段内已经存在预定数量的访问，则从高速缓冲存储器分配高速缓存条目以缓存数据。

9. 发明申请

US20110289257A1 METHOD AND APPARATUS FOR ACCESSING CACHE MEMORY 有权
标题翻译：用于访问高速缓存存储器的方法和设备
公开(公告)号：US20110289257A1
公开(公告)日：2011-11-24
申请号：US12784276
申请日：2010-05-20
申请人： Robert Hathaway , Evan Gewirtz
发明人： Robert Hathaway , Evan Gewirtz
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0888 , G06F12/12
摘要： A request for reading data from a memory location of a main memory is received, the memory location being identified by a physical memory address. In response to the request, a cache memory is accessed based on the physical memory address to determine whether the cache memory contains the data being requested. The data associated with the request is returned from the cache memory without accessing the memory location if there is a cache hit. The data associated is returned from the main memory if there is a cache miss. In response to the cache miss, it is determined whether there have been a number of accesses within a predetermined period of time. A cache entry is allocated from the cache memory to cache the data if there have been a predetermined number of accesses within the predetermined period of time.
摘要翻译：接收到从主存储器的存储器位置读取数据的请求，存储器位置由物理存储器地址标识。响应于该请求，基于物理存储器地址访问高速缓存存储器，以确定高速缓冲存储器是否包含正被请求的数据。如果存在高速缓存命中，与请求相关联的数据从高速缓冲存储器返回，而不访问存储器位置。如果存在高速缓存未命中，则从主存储器返回相关的数据。响应于高速缓存未命中，确定在预定时间段内是否存在多个访问。如果在预定时间段内已经存在预定数量的访问，则从高速缓冲存储器分配高速缓存条目以缓存数据。

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