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1. 发明授权

US08823077B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08823077B2
公开(公告)日：2014-09-02
申请号：US12929517
申请日：2011-01-31
申请人： Eun-Hong Lee , Seung-Hun Hong , Un-jeong Kim , Hyung-Woo Lee , Sung Myung
发明人： Eun-Hong Lee , Seung-Hun Hong , Un-jeong Kim , Hyung-Woo Lee , Sung Myung
IPC分类号： H01L29/788 , H01L51/10 , B82Y10/00 , H01L51/00 , H01L51/05
CPC分类号： H01L51/102 , B82Y10/00 , H01L51/0048 , H01L51/0541 , H01L51/105
摘要： A semiconductor device according to example embodiments may include a channel including a nanowire and a charge storage layer including nanoparticles. A twin gate structure including a first gate and a second gate may be formed on the charge storage layer. The semiconductor device may be a memory device or a diode.
摘要翻译：根据示例性实施例的半导体器件可以包括包括纳米线和包含纳米颗粒的电荷存储层的沟道。可以在电荷存储层上形成包括第一栅极和第二栅极的双栅极结构。半导体器件可以是存储器件或二极管。

2. 发明授权

US08455854B2 Nonvolatile memory device including amorphous alloy metal oxide layer and method of manufacturing the same 有权
标题翻译：包括非晶合金金属氧化物层的非易失性存储器件及其制造方法
公开(公告)号：US08455854B2
公开(公告)日：2013-06-04
申请号：US11704365
申请日：2007-02-09
申请人： Choong-Rae Cho , Sung-Il Cho , In-Kyeong Yoo , Eun-Hong Lee , Chang-Wook Moon
发明人： Choong-Rae Cho , Sung-Il Cho , In-Kyeong Yoo , Eun-Hong Lee , Chang-Wook Moon
IPC分类号： H01L47/00
CPC分类号： H01L27/2409 , H01L21/31691 , H01L29/47 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A nonvolatile memory device may include a lower electrode, an oxide layer including an amorphous alloy metal oxide disposed on the lower electrode, and a diode structure disposed on the oxide layer.
摘要翻译：非易失性存储器件可以包括下电极，包括设置在下电极上的非晶合金金属氧化物的氧化物层和设置在氧化物层上的二极管结构。

3. 发明授权

US08350262B2 Nonvolatile memory device and nonvolatile memory array including the same 有权
标题翻译：非易失性存储器件和包括其的非易失性存储器阵列
公开(公告)号：US08350262B2
公开(公告)日：2013-01-08
申请号：US12929121
申请日：2011-01-03
申请人： Myoung-Jae Lee , In-Kyeong Yoo , Eun-Hong Lee , Jong-Wan Kim , Dong-Chul Kim , Seung-Eon Ahn
发明人： Myoung-Jae Lee , In-Kyeong Yoo , Eun-Hong Lee , Jong-Wan Kim , Dong-Chul Kim , Seung-Eon Ahn
IPC分类号： H01L29/10 , H01L29/12
CPC分类号： H01L27/1021 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C2213/73
摘要： A nonvolatile memory device having self-presence diode characteristics, and/or a nonvolatile memory array including the nonvolatile memory device may be provided. The nonvolatile memory device may include a lower electrode, a first semiconductor oxide layer on the lower electrode, a second semiconductor oxide layer on the first semiconductor oxide layer, and/or an upper electrode on the second semiconductor oxide layer.
摘要翻译：可以提供具有自身存在二极管特性的非易失性存储器件和/或包括非易失性存储器件的非易失性存储器阵列。非易失性存储器件可以包括下电极，下电极上的第一半导体氧化物层，第一半导体氧化物层上的第二半导体氧化物层，和/或第二半导体氧化物层上的上电极。

4. 发明申请

US20070295950A1 Variable resistance random access memory device and a method of fabricating the same 有权
标题翻译：可变电阻随机存取存储器件及其制造方法
公开(公告)号：US20070295950A1
公开(公告)日：2007-12-27
申请号：US11702623
申请日：2007-02-06
申请人： Choong-Rae Cho , Eun-Hong Lee , Stefanovich Genrikh , El Mostafa Bourim
发明人： Choong-Rae Cho , Eun-Hong Lee , Stefanovich Genrikh , El Mostafa Bourim
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/146 , Y10S438/90
摘要： Provided is a variable resistance random access memory device having an n+ interfacial layer and a method of fabricating the same. The variable resistance random access memory device may include a lower electrode, an n+ interfacial layer on the lower electrode, a buffer layer on the n+ interfacial layer, an oxide layer on the buffer layer and having a variable resistance characteristic and an upper electrode on the oxide layer.
摘要翻译：提供了具有n +界面层的可变电阻随机存取存储器件及其制造方法。可变电阻随机存取存储器件可以包括下电极，下电极上的n +界面层，n +界面层上的缓冲层，缓冲层上的氧化物层和可变电阻特性上的上电极氧化层。

5. 发明申请

US20070252193A1 Non-volatile memory devices including variable resistance material 有权
标题翻译：包括可变电阻材料的非易失性存储器件
公开(公告)号：US20070252193A1
公开(公告)日：2007-11-01
申请号：US11785478
申请日：2007-04-18
申请人： Choong-Rae Cho , Eun-Hong Lee , El Mostafa Bourim , Chang-Wook Moon
发明人： Choong-Rae Cho , Eun-Hong Lee , El Mostafa Bourim , Chang-Wook Moon
IPC分类号： H01L29/788
CPC分类号： H01L27/101 , G11C11/5685 , G11C13/0007 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/52 , H01L29/24 , H01L29/8615 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/146
摘要： A non-volatile memory device comprises a first oxide layer, a second oxide layer and a buffer layer formed on a lower electrode. An upper electrode is formed on the buffer layer. In one example, the lower electrode is composed of at least one of Pt, Ru, Ir, IrOx and an alloy thereof, the second oxide layer is a transition metal oxide, the buffer layer is composed of a p-type oxide and the upper electrode is composed of a material selected from Ni, Co, Cr, W, Cu or an alloy thereof.
摘要翻译：非易失性存储器件包括形成在下电极上的第一氧化物层，第二氧化物层和缓冲层。在缓冲层上形成上电极。在一个示例中，下电极由Pt，Ru，Ir，IrOx及其合金中的至少一种构成，第二氧化物层是过渡金属氧化物，缓冲层由p型氧化物和上部电极由选自Ni，Co，Cr，W，Cu或其合金的材料构成。

6. 发明申请

US20070189065A1 Phase-change random access memory and programming method 有权
标题翻译：相变随机存取存储器和编程方法
公开(公告)号：US20070189065A1
公开(公告)日：2007-08-16
申请号：US11657649
申请日：2007-01-25
申请人： Dong-Seok Suh , Eun-Hong Lee , Jin-Seo Noh
发明人： Dong-Seok Suh , Eun-Hong Lee , Jin-Seo Noh
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/009 , G11C2013/0092 , G11C2213/77
摘要： A programming method for a phase-change random access memory (PRAM) may be provided. The programming method may include determining an amorphous state of a chalcogenide material using programming pulses to form programming areas having threshold voltages corresponding to logic high and logic low, and/or controlling a trailing edge of programming pulses during programming to control a quenching speed of the chalcogenide material so as to adjust a threshold voltage of the chalcogenide material. Accordingly, programming pulses corresponding to logic low or logic high may have uniform magnitudes regardless of a corresponding logic level. Accordingly, reliability of a PRAM device may be improved.
摘要翻译：可以提供用于相变随机存取存储器（PRAM）的编程方法。编程方法可以包括使用编程脉冲来确定硫族化物材料的非晶状态，以形成具有对应于逻辑高和逻辑低的阈值电压的编程区域，和/或在编程期间控制编程脉冲的后沿以控制编程脉冲的淬灭速度硫属化物材料，以便调节硫族化物材料的阈值电压。因此，对应于逻辑低或逻辑高的编程脉冲可以具有均匀的幅度，而与对应的逻辑电平无关。因此，可以提高PRAM装置的可靠性。

7. 发明申请

US20070165434A1 Resistive RAM having at least one varistor and methods of operating the same 有权
标题翻译：具有至少一个压敏电阻的电阻RAM及其操作方法
公开(公告)号：US20070165434A1
公开(公告)日：2007-07-19
申请号：US11655086
申请日：2007-01-19
申请人： Jung-Hyun Lee , Eun-Hong Lee , Sang-Jun Choi , In-Kyeong Yoo , Myoung-Jae Lee
发明人： Jung-Hyun Lee , Eun-Hong Lee , Sang-Jun Choi , In-Kyeong Yoo , Myoung-Jae Lee
IPC分类号： G11C27/00
CPC分类号： G11C13/003 , G11C13/0007 , G11C2213/32 , G11C2213/76
摘要： Resistive memory devices having at least one varistor and methods of operating the same are disclosed. The resistive memory device may include at least one bottom electrode line, at least one top electrode line crossing the at least one bottom electrode line, and at least one stack structure disposed at an intersection of the at least one top electrode line and the at least one bottom electrode line including a varistor and a data storage layer.
摘要翻译：公开了具有至少一个压敏电阻的电阻式存储器件及其操作方法。电阻式存储器件可以包括至少一个底部电极线，与至少一个底部电极线交叉的至少一个顶部电极线以及至少一个堆叠结构，该至少一个堆叠结构设置在至少一个顶部电极线和至少一个顶部电极线的交点处一个底部电极线包括变阻器和数据存储层。

8. 发明授权

US07626859B2 Phase-change random access memory and programming method 有权
标题翻译：相变随机存取存储器和编程方法
公开(公告)号：US07626859B2
公开(公告)日：2009-12-01
申请号：US11657649
申请日：2007-01-25
申请人： Dong-Seok Suh , Eun-Hong Lee , Jin-Seo Noh
发明人： Dong-Seok Suh , Eun-Hong Lee , Jin-Seo Noh
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/009 , G11C2013/0092 , G11C2213/77
摘要： A programming method for a phase-change random access memory (PRAM) may be provided. The programming method may include determining an amorphous state of a chalcogenide material using programming pulses to form programming areas having threshold voltages corresponding to logic high and logic low, and/or controlling a trailing edge of programming pulses during programming to control a quenching speed of the chalcogenide material so as to adjust a threshold voltage of the chalcogenide material. Accordingly, programming pulses corresponding to logic low or logic high may have uniform magnitudes regardless of a corresponding logic level. Accordingly, reliability of a PRAM device may be improved.
摘要翻译：可以提供用于相变随机存取存储器（PRAM）的编程方法。编程方法可以包括使用编程脉冲来确定硫族化物材料的非晶状态，以形成具有对应于逻辑高和逻辑低的阈值电压的编程区域，和/或在编程期间控制编程脉冲的后沿以控制编程脉冲的淬灭速度硫属化物材料，以便调节硫族化物材料的阈值电压。因此，对应于逻辑低或逻辑高的编程脉冲可以具有均匀的幅度，而与对应的逻辑电平无关。因此，可以提高PRAM装置的可靠性。

9. 发明授权

US07352037B2 Semiconductor device and random access memory having single gate electrode corresponding to a pair of channel regions 有权
标题翻译：具有对应于一对通道区域的单个栅电极的半导体器件和随机存取存储器
公开(公告)号：US07352037B2
公开(公告)日：2008-04-01
申请号：US11393750
申请日：2006-03-31
申请人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
发明人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
IPC分类号： H01L29/94
CPC分类号： H01L29/66795 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/11507 , H01L27/2436 , H01L29/785
摘要： A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.
摘要翻译：半导体器件可以包括半导体衬底上的至少一对散热片。可以在每个鳍中形成沟道区。半导体器件还可以包括对应于每对沟道区的栅电极，同时电连接到形成在相应散热片上的至少一个源中的每一个的源极接触插塞以及电连接到至少一个漏斗同时形成在相应的翅片上。

10. 发明申请

US20070290186A1 Non-volatile variable resistance memory device and method of fabricating the same 有权
标题翻译：非易失性可变电阻存储器件及其制造方法
公开(公告)号：US20070290186A1
公开(公告)日：2007-12-20
申请号：US11797519
申请日：2007-05-04
申请人： El Mostafa Bourim , Eun-Hong Lee , Choong-Rae Cho
发明人： El Mostafa Bourim , Eun-Hong Lee , Choong-Rae Cho
IPC分类号： H01L47/00
CPC分类号： H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/146
摘要： A non-volatile variable resistance memory device and a method of fabricating the same are provided. The non-volatile variable resistance memory device may include a lower electrode, a buffer layer on the lower electrode, an oxide layer on the buffer layer and an upper electrode on the oxide layer. The buffer layer may be composed of an oxide and the oxide layer may have variable resistance characteristics.
摘要翻译：提供了一种非易失性可变电阻存储器件及其制造方法。非挥发性可变电阻存储器件可以包括下电极，下电极上的缓冲层，缓冲层上的氧化物层和氧化物层上的上电极。缓冲层可由氧化物构成，氧化物层可具有可变电阻特性。

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