专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120112270A1 VERTICAL TRANSISTOR HAVING BURIED JUNCTION AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：具有接合连接的垂直晶体管及其制造方法
公开(公告)号：US20120112270A1
公开(公告)日：2012-05-10
申请号：US13252504
申请日：2011-10-04
申请人： Eun Shil PARK , Yong Seok EUN , Kyong Bong ROUH
发明人： Eun Shil PARK , Yong Seok EUN , Kyong Bong ROUH
IPC分类号： H01L29/78 , H01L21/336 , H01L21/265
CPC分类号： H01L29/7827 , H01L21/2257 , H01L21/26513 , H01L21/26586 , H01L21/32134 , H01L21/32139 , H01L27/10876 , H01L27/10888 , H01L29/0847 , H01L29/167 , H01L29/456 , H01L29/66666 , H01L2924/0002 , H01L2924/00
摘要： A buried junction is formed in a vertical transistor of a semiconductor device. Wall bodies are formed from a semiconductor substrate, the wall bodies protruding while having a first side surface and a second side surface in the opposite side of the first side surface; forming a one side contact mask having an opening which selectively opens a portion of the first side surface of the wall body; and forming a first impurity layer and a second impurity layer surrounding the first impurity layer by diffusing impurities having different diffusivities into the portion of the first side surface exposed to the opening.
摘要翻译：在半导体器件的垂直晶体管中形成掩埋结。壁体由半导体基板形成，壁体在第一侧表面的相对侧具有第一侧表面和第二侧表面而突出; 形成具有开口的一侧接触掩模，所述开口选择性地打开所述壁体的所述第一侧表面的一部分; 以及通过将具有不同扩散性的杂质扩散到暴露于所述开口的所述第一侧表面的部分中，形成围绕所述第一杂质层的第一杂质层和第二杂质层。

2. 发明申请

US20110306192A1 METHOD FOR FORMING IMPURITY REGION OF VERTICAL TRANSISTOR AND METHOD FOR FABRICATING VERTICAL TRANSISTOR USING THE SAME 有权
标题翻译：用于形成垂直晶体管的侵入区域的方法和使用其制造垂直晶体管的方法
公开(公告)号：US20110306192A1
公开(公告)日：2011-12-15
申请号：US13084220
申请日：2011-04-11
申请人： Yong Seok EUN , Tae Kyun KIM , Kyong Bong ROUH , Eun Shil PARK
发明人： Yong Seok EUN , Tae Kyun KIM , Kyong Bong ROUH , Eun Shil PARK
IPC分类号： H01L21/266
CPC分类号： H01L21/266 , H01L21/26513 , H01L21/26586 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.
摘要翻译：用于形成垂直晶体管的杂质区域的方法包括在半导体衬底内形成杂质离子结区域，并通过蚀刻形成杂质离子结区域的半导体衬底形成沟槽。执行蚀刻处理以去除杂质离子结区域的一部分，使得杂质离子接合区域的剩余部分暴露于沟槽的下侧壁以用作掩埋位线结区域。

3. 发明申请

US20120208364A1 METHOD FOR OPENING ONE-SIDE CONTACT REGION OF VERTICAL TRANSISTOR AND METHOD FOR FABRICATING ONE-SIDE JUNCTION REGION USING THE SAME 有权
标题翻译：用于打开垂直晶体管的单面接触区域的方法和使用该方法制造单面结区的方法
公开(公告)号：US20120208364A1
公开(公告)日：2012-08-16
申请号：US13161846
申请日：2011-06-16
申请人： Kyong Bong ROUH , Yong Seok EUN , Eun Shil PARK
发明人： Kyong Bong ROUH , Yong Seok EUN , Eun Shil PARK
IPC分类号： H01L21/28 , H01L21/311
CPC分类号： H01L21/32155 , H01L21/2236 , H01L21/2257 , H01L21/26586 , H01L21/31144 , H01L21/32134 , H01L27/10876 , H01L27/10888 , H01L29/66666 , H01L29/7827
摘要： A method for opening a one-side contact region of a vertical transistor is provided. The one-side contact region of the vertical transistor is opened using a polysilicon layer, a certain portion of which can be selectively removed by a selective ion implantation process. In order to selectively remove the polysilicon layer formed on one of both sides of an active region, at which the one-side contact is to be formed, impurity ion implantation is performed in a direction vertical to the polysilicon layer by a plasma doping process, and a tilt ion implantation using an existing ion implantation process is performed. In this manner, the polysilicon layer is selectively doped, and the undoped portion of the polysilicon layer is selectively removed.
摘要翻译：提供了一种用于打开垂直晶体管的单侧接触区域的方法。使用多晶硅层打开垂直晶体管的单面接触区域，通过选择性离子注入工艺可以选择性地去除其中的一部分。为了选择性地去除形成在要形成单面接触的有源区的两侧的多晶硅层，通过等离子体掺杂工艺在与多晶硅层垂直的方向上进行杂质离子注入，并且使用现有的离子注入工艺进行倾斜离子注入。以这种方式，选择性地掺杂多晶硅层，并且选择性地去除多晶硅层的未掺杂部分。

4. 发明申请

US20120208334A1 METHODS OF FABRICATING A DUAL POLYSILICON GATE AND METHODS OF FABRICATING A SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：制造双聚硅酮门的方法和使用其制造半导体器件的方法
公开(公告)号：US20120208334A1
公开(公告)日：2012-08-16
申请号：US13365462
申请日：2012-02-03
申请人： Kyong Bong ROUH , Yong Seok EUN
发明人： Kyong Bong ROUH , Yong Seok EUN
IPC分类号： H01L21/8238
CPC分类号： H01L21/82385 , H01L21/28114 , H01L21/823842 , H01L29/42376
摘要： Methods of forming a dual polysilicon gate are provided. The method includes forming a polysilicon layer doped with impurities of a first conductivity type on a substrate having a first region and a second region, forming a mask pattern that covers the polysilicon layer in the first region and leaves the polysilicon layer in the second region, injecting impurities of a second conductivity type into the polysilicon layer in the second region left exposed by the mask pattern. Removing the mask pattern, and patterning the polysilicon layer to form a first polysilicon pattern in the first region and a second polysilicon pattern in the second region. The second polysilicon pattern is formed to have protrusions that laterally protrude from sidewalls thereof. Subsequently, impurities of the second conductivity type are injected into the substrate in the second region and into the protrusions of the second polysilicon pattern.
摘要翻译：提供了形成双重多晶硅栅极的方法。该方法包括在具有第一区域和第二区域的衬底上形成掺杂有第一导电类型的杂质的多晶硅层，形成覆盖第一区域中的多晶硅层并在第二区域中离开多晶硅层的掩模图案，将第二导电类型的杂质注入到由掩模图案留下的第二区域中的多晶硅层中。去除掩模图案，以及图案化多晶硅层以在第一区域中形成第一多晶硅图案，在第二区域形成第二多晶硅图案。第二多晶硅图案被形成为具有从其侧壁横向突出的突起。随后，将第二导电类型的杂质注入到第二区域中的衬底中并注入到第二多晶硅图案的突起中。

5. 发明申请

US20130161767A1 SEMICONDUCTOR DEVICES HAVING POLYSILICON GATE PATTERNS AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：具有多晶硅栅格图案的半导体器件及其制造方法
公开(公告)号：US20130161767A1
公开(公告)日：2013-06-27
申请号：US13615312
申请日：2012-09-13
申请人： Kyong Bong ROUH , Yong Seok EUN , Young Jin SON
发明人： Kyong Bong ROUH , Yong Seok EUN , Young Jin SON
IPC分类号： H01L29/78 , H01L21/425
CPC分类号： H01L29/4941 , H01L21/28035 , H01L29/4925
摘要： A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern.
摘要翻译：一种在衬底上包括栅极绝缘图案的半导体器件，以及堆叠在与衬底相对的栅极绝缘图案侧的非晶硅图案和多晶硅图案的半导体栅极图案。非晶硅图案包括抑制杂质离子在半导体栅极图案中的扩散的抗扩散杂质。

6. 发明申请

US20120007171A1 SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL TRANSISTOR AND BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有垂直晶体管和凸点线的半导体存储器件及其制造方法
公开(公告)号：US20120007171A1
公开(公告)日：2012-01-12
申请号：US13077116
申请日：2011-03-31
申请人： Baek Mann KIM , Jun Ki KIM , Yong Seok EUN , Kyong Bong ROUH
发明人： Baek Mann KIM , Jun Ki KIM , Yong Seok EUN , Kyong Bong ROUH
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/10876 , H01L21/2257 , H01L27/10888 , H01L29/456 , H01L29/66666 , H01L29/7827
摘要： A semiconductor memory device includes an active region protruding upward from a substrate, wherein the active region is arranged next to a trench on the substrate, a first impurity region formed at an upper portion of the active region, a second impurity region formed at a lower portion of the active region, a gate dielectric layer formed along a side of the active region between the first impurity region and the second impurity region, a gate electrode layer formed on the gate dielectric layer, a buried bit line formed at a lower portion of the trench, and a polysilicon layer formed over the buried bit line, wherein the polysilicon layer electrically connects the buried bit line with the second impurity region.
摘要翻译：半导体存储器件包括从衬底向上突出的有源区，其中有源区布置在衬底上的沟槽旁边，形成在有源区的上部的第一杂质区，形成在下部的第二杂质区有源区的一部分，沿着第一杂质区和第二杂质区之间的有源区的一侧形成的栅介质层，形成在栅介质层上的栅电极层，形成在栅电介质层的下部的掩埋位线所述沟槽和形成在所述掩埋位线上的多晶硅层，其中所述多晶硅层将所述掩埋位线与所述第二杂质区电连接。

7. 发明申请

US20120208335A1 METHODS OF FABRICATING A SEMICONDUCTOR DEVICE HAVING LOW CONTACT RESISTANCE 审中-公开
标题翻译：制造具有低接触电阻的半导体器件的方法
公开(公告)号：US20120208335A1
公开(公告)日：2012-08-16
申请号：US13396355
申请日：2012-02-14
申请人： Kyong Bong ROUH , Ho Jin CHO , Yong Soo JOUNG
发明人： Kyong Bong ROUH , Ho Jin CHO , Yong Soo JOUNG
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814
摘要： Methods of fabricating a semiconductor device are provided. The method includes forming a first gate stack and a second gate stack on a first region and a second region of a substrate, respectively. The method may further comprise forming first impurity regions self-aligned with the first gate stack and second impurity regions self-aligned with the second gate stack in the substrate of the first region and in the substrate of the second region, respectively. First impurity ions may be injected into the first and second impurity regions, forming a mask pattern covering the first region and exposing the second region on the substrate where the first impurity ions are injected and second impurity ions having an opposite conductivity type to the first impurity ions may be injected into the second impurity regions exposed by the mask pattern using a plasma doping process. The mask pattern may then be removed.
摘要翻译：提供制造半导体器件的方法。该方法包括分别在衬底的第一区域和第二区域上形成第一栅极堆叠和第二栅极堆叠。该方法还可以包括分别在第一区域的衬底和第二区域的衬底中形成与第一栅极堆叠自对准的第一杂质区域和与第二栅极堆叠自对准的第二杂质区域。可以将第一杂质离子注入到第一和第二杂质区域中，形成覆盖第一区域的掩模图案，并暴露衬底上的第一杂质离子被注入的第二区域和具有相反导电类型的第二杂质离子与第一杂质可以使用等离子体掺杂工艺将离子注入到由掩模图案曝光的第二杂质区域中。然后可以去除掩模图案。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式