专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110204430A1 NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20110204430A1
公开(公告)日：2011-08-25
申请号：US13097479
申请日：2011-04-29
申请人： Se Jun KIM , Eun Seok CHOI , Kyoung Hwan PARK , Hyun Seung YOO , Myung Shik LEE , Young Ok HONG , Jung Ryul AHN , Yong Top KIM , Kyung Pil HWANG , Won Sic WOO , Jae Young PARK , Ki Hong LEE , Ki Seon PARK , Moon Sig JOO
发明人： Se Jun KIM , Eun Seok CHOI , Kyoung Hwan PARK , Hyun Seung YOO , Myung Shik LEE , Young Ok HONG , Jung Ryul AHN , Yong Top KIM , Kyung Pil HWANG , Won Sic WOO , Jae Young PARK , Ki Hong LEE , Ki Seon PARK , Moon Sig JOO
IPC分类号： H01L29/792 , B82Y99/00
CPC分类号： H01L29/513 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/792
摘要： A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
摘要翻译：提供了一种非易失性存储器件及其制造方法，以防止存储在电荷陷阱层中的电荷移动到相邻存储器单元。制造非易失性存储器件的方法包括在半导体衬底上形成第一电介质层，其中有源区由隔离层限定，在第一电介质层上形成电荷陷阱层，去除第一介电层和电荷陷阱层在隔离层上，在包括电荷陷阱层的隔离层上形成第二电介质层，并在第二介电层上形成导电层。

2. 发明申请

US20080225595A1 CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF 失效
标题翻译：充电陷阱型非易失性存储器件及其程序方法
公开(公告)号：US20080225595A1
公开(公告)日：2008-09-18
申请号：US11771632
申请日：2007-06-29
申请人： Eun Seok CHOI , Se Jun Kim , Kyoung Hwan Park , Hyun Seung Yoo
发明人： Eun Seok CHOI , Se Jun Kim , Kyoung Hwan Park , Hyun Seung Yoo
IPC分类号： G11C11/34
CPC分类号： G11C16/3454 , G11C16/0466
摘要： A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell.
摘要翻译：一种对电荷陷阱型非易失性存储器件进行编程的方法包括将程序脉冲施加到所选择的存储单元，向所选择的存储单元施加去除脉冲，以及将程序验证脉冲施加到存储单元。电荷陷阱型非易失性存储器件包括具有电荷陷阱存储单元的存储单元阵列，以及用于向电荷陷阱存储单元提供去除脉冲的高电压发生器。

3. 发明申请

US20080230830A1 NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080230830A1
公开(公告)日：2008-09-25
申请号：US12052914
申请日：2008-03-21
申请人： Se Jun KIM , Eun Seok CHOI , Kyoung Hwan PARK , Hyun Seung YOO , Myung Shik LEE , Young Ok HONG , Jung Ryul AHN , Yong Top KIM , Kyung Pil HWANG , Won Sic WOO , Jae Young PARK , Ki Hong LEE , Ki Seon PARK , Moon Sig JOO
发明人： Se Jun KIM , Eun Seok CHOI , Kyoung Hwan PARK , Hyun Seung YOO , Myung Shik LEE , Young Ok HONG , Jung Ryul AHN , Yong Top KIM , Kyung Pil HWANG , Won Sic WOO , Jae Young PARK , Ki Hong LEE , Ki Seon PARK , Moon Sig JOO
IPC分类号： H01L29/792 , H01L21/28 , H01L21/762
CPC分类号： H01L29/513 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/792
摘要： A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
摘要翻译：提供了一种非易失性存储器件及其制造方法，以防止存储在电荷陷阱层中的电荷移动到相邻存储器单元。制造非易失性存储器件的方法包括在半导体衬底上形成第一电介质层，其中有源区由隔离层限定，在第一电介质层上形成电荷陷阱层，去除第一介电层和电荷陷阱层在隔离层上，在包括电荷陷阱层的隔离层上形成第二电介质层，并在第二介电层上形成导电层。

4. 发明申请

US20130099306A1 3-D NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20130099306A1
公开(公告)日：2013-04-25
申请号：US13613839
申请日：2012-09-13
申请人： Eun Seok CHOI , Hyun Seung YOO
发明人： Eun Seok CHOI , Hyun Seung YOO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L29/66833 , H01L29/792
摘要： A three-dimensional (3-D) nonvolatile memory device includes a support protruded from a surface of a substrate and configured to have an inclined sidewall; channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the inclined sidewall of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; select lines formed over the channel structures; and a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines.

5. 发明申请

US20130100738A1 THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES 有权
标题翻译：三维非易失性存储器件
公开(公告)号：US20130100738A1
公开(公告)日：2013-04-25
申请号：US13599322
申请日：2012-08-30
申请人： Eun Seok CHOI
发明人： Eun Seok CHOI
IPC分类号： H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： H01L29/7926 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： A three-dimensional (3-D) nonvolatile memory device includes channel layers protruded from a substrate, word line structures configured to include word lines stacked over the substrate, first junctions and second junctions formed in the substrate between the word line structures adjacent to each other, source lines coupled to the first junctions, respectively, and well pickup lines coupled to the second junctions, respectively.
摘要翻译：三维（3-D）非易失性存储器件包括从衬底突出的沟道层，字线结构被配置为包括堆叠在衬底上的字线，形成在衬底中的与每个相邻的字线结构之间的衬底中的第一结和第二结分别耦合到第一结的源极线以及耦合到第二结的阱拾取线。

6. 发明申请

US20120300547A1 3-DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：三维非易失性存储器件及其制造方法
公开(公告)号：US20120300547A1
公开(公告)日：2012-11-29
申请号：US13477479
申请日：2012-05-22
申请人： Eun Seok CHOI
发明人： Eun Seok CHOI
IPC分类号： G11C16/04 , H01L21/336
CPC分类号： H01L29/66833 , G11C16/0483 , H01L21/28282 , H01L27/11565 , H01L27/11568 , H01L27/11582 , H01L29/7926
摘要： A non-volatile memory device comprising a plurality of strings each including a drain select transistor, drain-side memory cells, a pipe transistor, source-side memory cells, and a source select transistor coupled in series, wherein the plurality of strings are arranged in a first direction and a second direction, and the strings arranged in the second direction form each of string columns; a plurality of bit lines extended in the second direction and coupled to the drain select transistors of the strings included in each string column; and a plurality of source lines extended in the first direction and in common coupled to the source select transistors of strings adjacent to each other in the second direction, wherein strings included in one of the string columns are staggered in the first direction and each of the string columns are coupled to at least two of the bit lines.
摘要翻译：一种非易失性存储器件，包括多个串，每个串均包括漏极选择晶体管，漏极侧存储单元，管状晶体管，源极侧存储单元和串联耦合的源极选择晶体管，其中多个串排列沿第一方向和第二方向，并且沿着第二方向布置的弦形成每个弦列; 多个位线在第二方向上延伸并耦合到每个串列中包括的串的漏极选择晶体管; 以及多个源极线，沿着第一方向延伸并且共同地耦合到在第二方向上彼此相邻的串的源选择晶体管，其中包括在串列之一中的串在第一方向上交错，并且每个串列耦合到至少两个位线。

7. 发明申请

US20130194869A1 THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE 有权
标题翻译：三维非易失性存储器件
公开(公告)号：US20130194869A1
公开(公告)日：2013-08-01
申请号：US13605942
申请日：2012-09-06
申请人： Eun Seok CHOI , Jung Ryul Ahn , Se Hoon Kim , Young Dae Park , In Geun Lim , Jung Seok Oh
发明人： Eun Seok CHOI , Jung Ryul Ahn , Se Hoon Kim , Young Dae Park , In Geun Lim , Jung Seok Oh
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , H01L27/11565 , H01L27/11582
摘要： A three-dimensional (3-D) non-volatile memory device according to embodiment of the present invention includes a plurality of bit lines, at least one string row extending in a first direction coupled to the bit lines and including 2N strings, wherein the N includes a natural number, a common source selection line configured to control source selection transistors of the 2N strings included in a memory block, a first common drain selection line configured to control drain selection transistors of a first string and a 2N-th string among the 2N strings included in a memory block, and N−1 second common drain selection lines configured to control drain selection transistors of adjacent strings in the first direction among remaining strings other than the first string and the 2N-th string.
摘要翻译：根据本发明的实施例的三维（3-D）非易失性存储器件包括多个位线，至少一个串行沿第一方向延伸，耦合到位线并包括2N个字符串，其中， N包括自然数，被配置为控制包括在存储块中的2N串的源选择晶体管的公共源选择线，被配置为控制第一串的漏极选择晶体管和第2N串的第2N串的第一公共漏极选择线包括在存储块中的2N个串，以及N-1个第二公共漏极选择线，被配置为控制除第一串和第2N个串之外的剩余串之中的第一方向上的相邻串的漏极选择晶体管。

8. 发明申请

US20120211823A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120211823A1
公开(公告)日：2012-08-23
申请号：US13397248
申请日：2012-02-15
申请人： Se Yun LIM , Eun Seok CHOI
发明人： Se Yun LIM , Eun Seok CHOI
IPC分类号： H01L27/105 , H01L21/8239 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11573 , H01L29/7926
摘要： A semiconductor memory device includes a lower select transistor formed within a semiconductor substrate, memory cells stacked over the lower select transistors, and an upper select transistor formed over the memory cells.
摘要翻译：半导体存储器件包括形成在半导体衬底内的下选择晶体管，堆叠在下选择晶体管上的存储单元，以及形成在存储单元上的上选择晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式