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1. 发明申请

US20070058452A1 Voltage glitch detection circuits and methods thereof 有权
标题翻译：电压毛刺检测电路及其方法
公开(公告)号：US20070058452A1
公开(公告)日：2007-03-15
申请号：US11434933
申请日：2006-05-17
申请人： Eui-Seung Kim , Jung-Hyun Kim
发明人： Eui-Seung Kim , Jung-Hyun Kim
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/02 , G11C7/06 , G11C7/1063 , G11C29/026
摘要： Voltage glitch detection circuits and methods thereof. In a first example, the voltage glitch detection circuit may include a monitoring memory array including at least one memory cell storing reference data, a monitoring sense amplifier receiving stored reference data from the monitoring memory array, amplifying the received stored reference data in response to an operation control signal and outputting data based on the reference data, a data storage circuit including at least one latch to store the reference data and a comparator circuit receiving and comparing the data output from the monitoring sense amplifier and the stored reference data from the data storage circuit, and outputting a detection signal based on the comparison. In a second example, the voltage glitch detection circuit may include a first storage unit configured to latch a first voltage, a second storage unit configured to latch a second voltage, a first comparator circuit first comparing the latched first voltage with a first reference voltage and outputting a first comparison result, a second compariator circuit second comparing the second voltage with a second reference voltage and outputting a second comparison result and a third comparator circuit third comparing the first and second comparison results and outputting a reset detection signal based on the third comparison.
摘要翻译：电压毛刺检测电路及其方法。在第一示例中，电压毛刺检测电路可以包括监视存储器阵列，其包括存储参考数据的至少一个存储器单元，监视读出放大器，从监视存储器阵列接收存储的参考数据，响应于操作控制信号，并且基于参考数据输出数据;数据存储电路，包括至少一个用于存储参考数据的锁存器;以及比较器电路，用于接收和比较来自监视读出放大器的数据和来自数据存储器的存储的参考数据电路，并且基于该比较输出检测信号。在第二示例中，电压毛刺检测电路可以包括被配置为锁存第一电压的第一存储单元，被配置为锁存第二电压的第二存储单元，第一比较器电路，首先将锁存的第一电压与第一参考电压进行比较;以及输出第一比较结果，第二比较器电路，将第二电压与第二参考电压进行比较，并输出第二比较结果;以及第三比较器电路，其对第一和第二比较结果进行比较，并输出基于第三比较的复位检测信号。

2. 发明授权

US07483328B2 Voltage glitch detection circuits and methods thereof 有权
标题翻译：电压毛刺检测电路及其方法
公开(公告)号：US07483328B2
公开(公告)日：2009-01-27
申请号：US11434933
申请日：2006-05-17
申请人： Eui-Seung Kim , Jung-Hyun Kim
发明人： Eui-Seung Kim , Jung-Hyun Kim
IPC分类号： G11C5/01
CPC分类号： G11C7/1051 , G11C7/02 , G11C7/06 , G11C7/1063 , G11C29/026
摘要： Voltage glitch detection circuits and methods thereof. The voltage glitch detection circuit may include a monitoring memory array including at least one memory cell storing reference data, a monitoring sense amplifier receiving stored reference data from the monitoring memory array, amplifying the received stored reference data in response to an operation control signal and outputting data based on the reference data, a data storage circuit including at least one latch to store the reference data and a comparator circuit receiving and comparing the data output from the monitoring sense amplifier and the stored reference data from the data storage circuit, and outputting a detection signal based on the comparison. The voltage glitch detection circuit may include a first storage unit configured to latch a first voltage, a second storage unit configured to latch a second voltage, a first comparator circuit first comparing the latched first voltage with a first reference voltage and outputting a first comparison result, a second compariator circuit second comparing the second voltage with a second reference voltage and outputting a second comparison result and a third comparator circuit third comparing the first and second comparison results and outputting a reset detection signal based on the third comparison.
摘要翻译：电压毛刺检测电路及其方法。电压毛刺检测电路可以包括监视存储器阵列，其包括存储参考数据的至少一个存储器单元，监视读出放大器，接收来自监视存储器阵列的存储的参考数据，响应于操作控制信号放大所接收的存储的参考数据并输出基于参考数据的数据的数据存储电路，包括用于存储参考数据的至少一个锁存器的数据存储电路;以及比较器电路，接收和比较来自监视读出放大器的数据和来自数据存储电路的存储的参考数据，检测信号基于比较。电压毛刺检测电路可以包括被配置为锁存第一电压的第一存储单元，被配置为锁存第二电压的第二存储单元，第一比较器电路，首先将锁存的第一电压与第一参考电压进行比较，并输出第一比较结果第二比较器电路，其将所述第二电压与第二参考电压进行比较，并输出第二比较结果;以及第三比较器电路，其对所述第一和第二比较结果进行比较，并输出基于所述第三比较的复位检测信号。

3. 发明申请

US20070176706A1 Apparatus and method for adaptive demodulation of PWM signal 有权
标题翻译： PWM信号自适应解调的装置和方法
公开(公告)号：US20070176706A1
公开(公告)日：2007-08-02
申请号：US11636187
申请日：2006-12-08
申请人： Eui-Seung Kim
发明人： Eui-Seung Kim
IPC分类号： H03K7/08
CPC分类号： H03K9/08
摘要： A demodulator for processing a PWM (pulse width modulation) signal includes a variable capacitor, a charging unit, a discharging unit, and a tuner. The charging and discharging units charge or discharge the variable capacitor depending on the PWM signal. The tuner determines a capacitance of the variable capacitor and a discharge current of the discharging unit for proper operation of the demodulator in various RF environments.
摘要翻译：用于处理PWM（脉宽调制）信号的解调器包括可变电容器，充电单元，放电单元和调谐器。充放电单元根据PWM信号对可变电容器进行充放电。调谐器确定可变电容器的电容和放电单元的放电电流，以便在各种RF环境中适当地操作解调器。

4. 发明申请

US20070053515A1 Semiconductor device using a read-only memory (ROM) scrambling/descrambling method, and a method of operating the same 审中-公开
标题翻译：使用只读存储器（ROM）加扰/解扰法的半导体器件及其操作方法
公开(公告)号：US20070053515A1
公开(公告)日：2007-03-08
申请号：US11499153
申请日：2006-08-04
申请人： Eui-Seung Kim , Jong-Cheol Kim
发明人： Eui-Seung Kim , Jong-Cheol Kim
IPC分类号： H04N7/167
CPC分类号： G11C7/24
摘要： A semiconductor device includes a processor, a read-only memory (ROM), a key generator, and a restoration unit. The ROM stores scrambled or encrypted run code and key generation information. The key generator generates a key using the key generation information. The restoration unit restores original run code by descrambling the scrambled run code or decrypting the encrypted run code using the generated key.
摘要翻译：半导体器件包括处理器，只读存储器（ROM），密钥发生器和恢复单元。 ROM存储加密或加密的运行代码和密钥生成信息。密钥生成器使用密钥生成信息生成密钥。恢复单元通过解扰加扰的运行代码或使用生成的密钥解密加密的运行代码来恢复原始运行代码。

5. 发明授权

US07471143B2 Apparatus and method for adaptive demodulation of PWM signal 有权
标题翻译： PWM信号自适应解调的装置和方法
公开(公告)号：US07471143B2
公开(公告)日：2008-12-30
申请号：US11636187
申请日：2006-12-08
申请人： Eui-Seung Kim
发明人： Eui-Seung Kim
IPC分类号： H03K9/08
CPC分类号： H03K9/08
摘要： A demodulator for processing a PWM (pulse width modulation) signal includes a variable capacitor, a charging unit, a discharging unit, and a tuner. The charging and discharging units charge or discharge the variable capacitor depending on the PWM signal. The tuner determines a capacitance of the variable capacitor and a discharge current of the discharging unit for proper operation of the demodulator in various RF environments.
摘要翻译：用于处理PWM（脉宽调制）信号的解调器包括可变电容器，充电单元，放电单元和调谐器。充放电单元根据PWM信号对可变电容器进行充放电。调谐器确定可变电容器的电容和放电单元的放电电流，以便在各种RF环境中适当地操作解调器。

6. 发明申请

US20080228961A1 SYSTEM INCLUDING VIRTUAL DMA AND DRIVING METHOD THEREOF 审中-公开
标题翻译：包括虚拟DMA及其驱动方法的系统
公开(公告)号：US20080228961A1
公开(公告)日：2008-09-18
申请号：US12049434
申请日：2008-03-17
申请人： Eui-Seung Kim
发明人： Eui-Seung Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A system having a virtual direct memory access (DMA) and a driving method thereof, in which the system includes a central processing unit (CPU), a plurality of intellectual property units (IPs), and a virtual DMA controlling data to be transferred from a first IP unit to a second IP unit according to select information that, selects the first and second IP units of the plurality of IP units, wherein the CPU provides the select information to the virtual DMA. As an example, the first IP transfers data and the second IP receives the data.
摘要翻译：一种具有虚拟直接存储器访问（DMA）及其驱动方法的系统，其中系统包括中央处理单元（CPU），多个知识产权单元（IP）以及要从根据选择信息的第一IP单元到第二IP单元，所述选择信息选择多个IP单元中的第一和第二IP单元，其中CPU向虚拟DMA提供选择信息。作为示例，第一IP传送数据和第二IP接收数据。

7. 发明授权

US08904251B2 Semiconductor device and test system for testing the same 有权
标题翻译：半导体器件和测试系统的测试相同
公开(公告)号：US08904251B2
公开(公告)日：2014-12-02
申请号：US13414955
申请日：2012-03-08
申请人： Eui-Seung Kim
发明人： Eui-Seung Kim
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318547
摘要： A semiconductor device includes a test pattern decoding unit and a scan chain unit. The test pattern receives a scan-in pattern from an external test device and generates a test pattern based on the scan-in pattern and a scan-out pattern. The scan-in pattern is decoded based on a seed pattern and an expectation pattern. The scan chain unit performs logical operation based on the test pattern and feedbacks the scan-out pattern to the test pattern decoding unit.
摘要翻译：半导体器件包括测试图案解码单元和扫描链单元。测试模式从外部测试设备接收扫描模式，并根据扫描模式和扫描模式生成测试模式。基于种子模式和期望模式对扫描模式进行解码。扫描链单元基于测试图案执行逻辑运算，并将扫描模式反馈到测试图案解码单元。

8. 发明授权

US07852166B2 Relaxation oscillator for compensating system delay 有权
标题翻译：用于补偿系统延迟的松弛振荡器
公开(公告)号：US07852166B2
公开(公告)日：2010-12-14
申请号：US12288512
申请日：2008-10-21
申请人： Eui-Seung Kim
发明人： Eui-Seung Kim
IPC分类号： H03B5/24 , H03K3/02 , H03K3/023 , H03K3/0233 , H03K3/027 , H03K3/037 , H03L1/00
CPC分类号： H03K3/0231 , H03L7/099
摘要： A relaxation oscillator compensates for system delay. The relaxation oscillator includes first and second input signal units that generates first and second capacitor voltages, a delay compensation unit that receives a reference voltage and the first and second capacitor voltages and that generates a compensation voltage. In certain embodiments, a voltage generating unit applies the reference voltage to the delay compensation unit, and a latch unit stores first and second comparison signals compared by the first and second input signal units and transmits a clock signal and a inverted clock signal to the first and second input signal units. The first and second input signal units compare the first and second capacitor voltages with a compensation voltage transmitted from the delay compensation unit.
摘要翻译：松弛振荡器补偿系统延迟。张弛振荡器包括产生第一和第二电容器电压的第一和第二输入信号单元，接收参考电压和第一和第二电容器电压并产生补偿电压的延迟补偿单元。在某些实施例中，电压产生单元将参考电压施加到延迟补偿单元，并且锁存单元存储由第一和第二输入信号单元比较的第一和第二比较信号，并将时钟信号和反相时钟信号发送到第一以及第二输入信号单元。第一和第二输入信号单元将第一和第二电容器电压与从延迟补偿单元发送的补偿电压进行比较。

9. 发明申请

US20090194598A1 SMART CARD SYSTEM AND OPERATING METHOD THEREOF 失效
标题翻译：智能卡系统及其操作方法
公开(公告)号：US20090194598A1
公开(公告)日：2009-08-06
申请号：US12353364
申请日：2009-01-14
申请人： Eui-Seung Kim , Jong-Cheol Kim
发明人： Eui-Seung Kim , Jong-Cheol Kim
IPC分类号： G06K19/067
CPC分类号： G06K19/073
摘要： A smart card system having: a smart card including a security logic circuit to detect an external attack; and a reader communicating with the smart card. The security logic circuit detects the external attack by measuring the external input capacitance through an input/output pad of the smart card and comparing the external input capacitance to the input capacitance of the reader. This improves the security of the smart card system.
摘要翻译：一种智能卡系统，具有：智能卡，其包括用于检测外部攻击的安全逻辑电路; 以及与智能卡通信的读取器。安全逻辑电路通过智能卡的输入/输出焊盘测量外部输入电容并将外部输入电容与读取器的输入电容进行比较来检测外部攻击。这提高了智能卡系统的安全性。

10. 发明授权

US07085979B2 Voltage-glitch detection device and method for securing integrated circuit device from voltage glitch attack 有权
公开(公告)号：US07085979B2
公开(公告)日：2006-08-01
申请号：US10443427
申请日：2003-05-22
申请人： Chan-Yong Kim , Sang-Joo Jun , Eui-Seung Kim
发明人： Chan-Yong Kim , Sang-Joo Jun , Eui-Seung Kim
IPC分类号： G01R31/28
CPC分类号： G11C16/225 , G06K19/073 , G06K19/07363 , G11C5/143
摘要： A voltage-glitch detection circuit includes a voltage comparator having two input terminals with different capacitance resistance charge/discharge time. Voltage dividers are coupled to the two input terminals of the voltage comparator respectively, and commonly receive a supply voltage. One of the voltage dividers is supplied to the voltage comparator as a reference voltage of the voltage comparator, and the other is supplied as a glitch detection voltage to the voltage comparator.

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