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1. 发明授权

US07724485B2 N-channel ESD clamp with improved performance 有权
标题翻译： N沟道ESD钳位具有改进的性能
公开(公告)号：US07724485B2
公开(公告)日：2010-05-25
申请号：US11738336
申请日：2007-04-20
申请人： Eugene Worley , Vivek Mohan , Reza Jalilizeinali
发明人： Eugene Worley , Vivek Mohan , Reza Jalilizeinali
IPC分类号： H02H9/00
CPC分类号： H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection circuit uses two N-channel field effect transistors (NFETs) to conduct ESD current from a first to a second supply node. During the ESD event, an ESD detection circuit couples the gates of both NFETs to the first supply node through separate conductive paths. In one novel aspect, an RC trigger circuit includes a capacitance that is charged through a resistance. The resistance involves a P-channel transistor whose gate is coupled to the gate of the second NFET. During a normal power-up condition, the P-channel transistor is conductive, thereby preventing the RC trigger from triggering if the supply voltage VDD were to rise rapidly. In another novel aspect, a novel level-shifting inverter drives the second NFET. The level-shifting inverter uses a pull down resistor to avoid snap-back and also isolates the gate of the second NFET from a capacitively loaded third supply node.
摘要翻译：静电放电（ESD）保护电路使用两个N沟道场效应晶体管（NFET）来传导来自第一至第二供电节点的ESD电流。在ESD事件期间，ESD检测电路通过单独的导电路径将两个NFET的栅极耦合到第一电源节点。在一个新颖的方面，RC触发电路包括通过电阻充电的电容。电阻涉及其栅极耦合到第二NFET的栅极的P沟道晶体管。在正常上电状态下，P沟道晶体管导通，如果电源电压VDD快速上升，则可防止RC触发。在另一个新颖的方面，新颖的电平移位逆变器驱动第二NFET。电平转换逆变器使用下拉电阻来避免卡扣，并且还将第二NFET的栅极与电容加载的第三电源节点隔离。

2. 发明申请

US20080049365A1 N-CHANNEL ESD CLAMP WITH IMPROVED PERFORMANCE 有权
标题翻译：具有改进性能的N沟道ESD钳位
公开(公告)号：US20080049365A1
公开(公告)日：2008-02-28
申请号：US11738336
申请日：2007-04-20
申请人： Eugene Worley , Vivek Mohan , Reza Jalilizeinali
发明人： Eugene Worley , Vivek Mohan , Reza Jalilizeinali
IPC分类号： H02H9/00
CPC分类号： H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection circuit uses two N-channel field effect transistors (NFETs) to conduct ESD current from a first to a second supply node. During the ESD event, an ESD detection circuit couples the gates of both NFETs to the first supply node through separate conductive paths. In one novel aspect, an RC trigger circuit includes a capacitance that is charged through a resistance. The resistance involves a P-channel transistor whose gate is coupled to the gate of the second NFET. During a normal power-up condition, the P-channel transistor is conductive, thereby preventing the RC trigger from triggering if the supply voltage VDD were to rise rapidly. In another novel aspect, a novel level-shifting inverter drives the second NFET. The level-shifting inverter uses a pull down resistor to avoid snap-back and also isolates the gate of the second NFET from a capacitively loaded third supply node.
摘要翻译：静电放电（ESD）保护电路使用两个N沟道场效应晶体管（NFET）来传导来自第一至第二供电节点的ESD电流。在ESD事件期间，ESD检测电路通过单独的导电路径将两个NFET的栅极耦合到第一电源节点。在一个新颖的方面，RC触发电路包括通过电阻充电的电容。电阻涉及其栅极耦合到第二NFET的栅极的P沟道晶体管。在正常上电状态下，P沟道晶体管导通，如果电源电压VDD快速上升，则可防止RC触发。在另一个新颖的方面，新颖的电平移位逆变器驱动第二NFET。电平转换逆变器使用下拉电阻来避免卡扣，并且还将第二NFET的栅极与电容加载的第三电源节点隔离。

3. 发明申请

US20050029597A1 Ballasting MOSFETs using staggered and segmented diffusion regions 失效
标题翻译：使用交错和分段扩散区域的镇流MOSFET
公开(公告)号：US20050029597A1
公开(公告)日：2005-02-10
申请号：US10637324
申请日：2003-08-08
申请人： Eugene Worley
发明人： Eugene Worley
IPC分类号： H01L27/02 , H01L29/06 , H01L29/08 , H01L29/76 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/0692 , H01L29/0696 , H01L29/78 , H01L29/7835
摘要： An ESD protection circuit includes a field effect transistor device configured such that current flowing through a hot spot filament formed in a gate region must flow in a non-linear path from a drain contact to a source contact. Source diffusion areas are segmented and staggered relative to drain diffusion areas in order to provide the non-linear current path.
摘要翻译： ESD保护电路包括场效应晶体管器件，其被配置为使流过形成在栅极区域中的热点灯丝的电流必须以从漏极接触到源极接触的非线性路径流动。源极扩散区域相对于漏扩散区域被分段和交错，以便提供非线性电流路径。

4. 发明授权

US07804669B2 Stacked ESD protection circuit having reduced trigger voltage 有权
标题翻译：堆叠的ESD保护电路具有降低的触发电压
公开(公告)号：US07804669B2
公开(公告)日：2010-09-28
申请号：US11737537
申请日：2007-04-19
申请人： Eugene Worley
发明人： Eugene Worley
IPC分类号： H02H3/22
CPC分类号： H01L27/0266
摘要： A stacked gate-coupled N-channel field effect transistor (GCNFET) electrostatic discharge (ESD) protection circuit involves a stack of stages. Each stage has an NFET whose body is coupled to its source. A resistor is coupled between the gate and the source. A current path is provided from a supply voltage node to the gate of each NFET such that during an ESD event, a current will flow across the resistor of the stage and induce triggering. In one embodiment, an NFET stage that is isolated from the supply voltage node by and other stage has an associated capacitance structure. During the transient voltage condition of the ESD event, current flows from the supply voltage node, through the capacitance structure and to the gate, and then through the resistor, thereby initiating triggering. The GCNFET ESD protection circuit has a trigger voltage that is less than twenty percent higher than its holding voltage.
摘要翻译：堆叠栅极耦合N沟道场效应晶体管（GCNFET）静电放电（ESD）保护电路涉及一叠级。每个阶段都有一个NFET，其主体与源极耦合。电阻器连接在栅极和源极之间。从电源电压节点向每个NFET的栅极提供电流路径，使得在ESD事件期间，电流将流过级的电阻器并且引起触发。在一个实施例中，与电源电压节点隔离的NFET级与其它级具有相关联的电容结构。在ESD事件的瞬态电压状态期间，电流从电源电压节点通过电容结构流向栅极，然后通过电阻，从而启动触发。 GCNFET ESD保护电路具有比其保持电压低20％的触发电压。

5. 发明申请

US20080259511A1 Stacked ESD Protection Circuit Having Reduced Trigger Voltage 有权
标题翻译：堆叠的ESD保护电路具有降低的触发电压
公开(公告)号：US20080259511A1
公开(公告)日：2008-10-23
申请号：US11737537
申请日：2007-04-19
申请人： Eugene Worley
发明人： Eugene Worley
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： A stacked gate-coupled N-channel field effect transistor (GCNFET) electrostatic discharge (ESD) protection circuit involves a stack of stages. Each stage has an NFET whose body is coupled to its source. A resistor is coupled between the gate and the source. A current path is provided from a supply voltage node to the gate of each NFET such that during an ESD event, a current will flow across the resistor of the stage and induce triggering. In one embodiment, an NFET stage that is isolated from the supply voltage node by and other stage has an associated capacitance structure. During the transient voltage condition of the ESD event, current flows from the supply voltage node, through the capacitance structure and to the gate, and then through the resistor, thereby initiating triggering. The GCNFET ESD protection circuit has a trigger voltage that is less than twenty percent higher than its holding voltage.
摘要翻译：堆叠栅极耦合N沟道场效应晶体管（GCNFET）静电放电（ESD）保护电路涉及一叠级。每个阶段都有一个NFET，其主体与源极耦合。电阻器连接在栅极和源极之间。从电源电压节点向每个NFET的栅极提供电流路径，使得在ESD事件期间，电流将流过级的电阻器并且引起触发。在一个实施例中，与电源电压节点隔离的NFET级与其它级具有相关联的电容结构。在ESD事件的瞬态电压状态期间，电流从电源电压节点通过电容结构流向栅极，然后通过电阻，从而启动触发。 GCNFET ESD保护电路具有比其保持电压低20％的触发电压。

6. 发明申请

US20060242350A1 Opto-couplers for communication bus interfaces using low efficiency silicon based LEDs 审中-公开
标题翻译：用于使用低效率硅基LED的通信总线接口的光耦合器
公开(公告)号：US20060242350A1
公开(公告)日：2006-10-26
申请号：US11409794
申请日：2006-04-22
申请人： Eugene Worley
发明人： Eugene Worley
IPC分类号： G06F13/14
CPC分类号： H04B10/801
摘要： This invention describes a means by which a communication data bus can be electrically isolated from noise generating electrical devices such as electromagnetic actuators, which are controlled by data from the bus, using a single integrated circuit package. Specifically, an all silicon optically isolated interface within the package is used to galvanic insulate the circuitry associated with the data bus interface from the circuitry operating or receiving data from devices such as motors, sensors, etc. that are connected to a noisy environment.
摘要翻译：本发明描述了一种通过数据总线与使用单个集成电路封装的来自总线的数据控制的诸如电磁致动器的噪声产生电气设备电隔离的方式。具体来说，封装内的全硅光学隔离接口用于将与数据总线接口相关联的电路与来自连接到嘈杂环境的诸如电动机，传感器等的设备操作或接收数据的电路进行电流绝缘。

7. 发明申请

US20050152081A1 ESD protection for integrated circuits having ultra thin gate oxides 有权
标题翻译：具有超薄栅极氧化物的集成电路的ESD保护
公开(公告)号：US20050152081A1
公开(公告)日：2005-07-14
申请号：US10990641
申请日：2004-11-16
申请人： Eugene Worley
发明人： Eugene Worley
IPC分类号： H01L27/02 , H02H9/00 , H02H9/04
CPC分类号： H01L27/0251 , H01L27/0292
摘要： According to an exemplary embodiment, an integrated circuit includes a first circuit block having a first power bus. The integrated circuit further includes a second circuit block having a second power bus, where the first power bus is isolated from the second power bus. The integrated circuit further includes a first dedicated ESD bus, where the first dedicated ESD bus provides a discharge path from the first power bus to the second power bus and from the second power bus to the first power bus. The first power bus can be coupled to the first dedicated ESD bus by a first pair to bi-directional diodes, and the second power bus can be coupled to the first dedicated ESD bus by a second pair of bi-directional diodes.
摘要翻译：根据示例性实施例，集成电路包括具有第一电力总线的第一电路块。集成电路还包括具有第二电力总线的第二电路块，其中第一电力总线与第二电力总线隔离。集成电路还包括第一专用ESD总线，其中第一专用ESD总线提供从第一电力总线到第二电力总线以及从第二电力总线到第一电力总线的放电路径。第一电源总线可以通过第一对双向二极管耦合到第一专用ESD总线，并且第二电源总线可以通过第二对双向二极管耦合到第一专用ESD总线。

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