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1. 发明申请

US20050071794A1 Methods for modeling latch transparency 有权
标题翻译：锁定透明度建模方法
公开(公告)号：US20050071794A1
公开(公告)日：2005-03-31
申请号：US10962121
申请日：2004-10-08
申请人： Erwin Behnen , Jeffrey Soreff , James Warnock , Dieter Wendel
发明人： Erwin Behnen , Jeffrey Soreff , James Warnock , Dieter Wendel
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5022
摘要： In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种方法，包括以下步骤：（1）接收具有多个锁存器的电路设计; 以及（2）允许电路设计的一个或多个闩锁在电路设计的定时行为建模期间被局部处理为呈现闩锁透明度。提供了许多其他方面。

2. 发明申请

US20050071790A1 Methods for modeling latch transparency 失效
公开(公告)号：US20050071790A1
公开(公告)日：2005-03-31
申请号：US10672500
申请日：2003-09-26
申请人： Erwin Behnen , Jeffrey Soreff , James Warnock , Dieter Wendel
发明人： Erwin Behnen , Jeffrey Soreff , James Warnock , Dieter Wendel
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5022
摘要： In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.

3. 发明申请

US20060031797A1 Method of timing model abstraction for circuits containing simultaneously switching internal signals 失效
标题翻译：包含同时切换内部信号的电路的定时模型抽象方法
公开(公告)号：US20060031797A1
公开(公告)日：2006-02-09
申请号：US10897349
申请日：2004-07-22
申请人： Jeffrey Soreff , James Warnock
发明人： Jeffrey Soreff , James Warnock
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： The present invention provides for determining arrival times in a circuit. An arrival time for a main signal is assigned. An arrival time for a secondary signal is assigned. It is determined whether a test is for an early arrival or for a later arrival. If the test type is for a late arrival, it is determined whether the arrival time for the secondary signal is later than for the first signal. If the test type is for an early arrival, it is determined whether the arrival time for the secondary signal is earlier than for the first signal. If the test type is for the late arrival and the arrival time for the secondary signal is later than for the first signal, assuming maximum interference between the signals. If the test type is for the late arrival and the arrival time for the secondary signal is not later than for the first signal, calculating the actual interference between the signals.
摘要翻译：本发明提供了确定电路中的到达时间。分配主信号的到达时间。分配辅助信号的到达时间。确定测试是提前到达还是稍后到达。如果测试类型是迟到的，则确定辅助信号的到达时间是否晚于第一信号。如果测试类型是用于提前到达，则确定辅助信号的到达时间是否早于第一信号。如果测试类型是迟到的，并且辅助信号的到达时间晚于第一信号，则假定信号之间的最大干扰。如果测试类型为迟到，并且次要信号的到达时间不晚于第一信号，则计算信号之间的实际干扰。

4. 发明授权

US07643981B2 Pulse waveform timing in EinsTLT templates 失效
标题翻译： EinsTLT模板中的脉冲波形定时
公开(公告)号：US07643981B2
公开(公告)日：2010-01-05
申请号：US10897347
申请日：2004-07-22
申请人： Sang Y. Lee , Vasant B. Rao , Jeffrey Soreff , James Warnock , David Winston
发明人： Sang Y. Lee , Vasant B. Rao , Jeffrey Soreff , James Warnock , David Winston
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention provides for simulating signal transitions. Circuit characteristics are generated. Circuit characteristics are loaded into memory. Circuit behaviour is simulated. A non-leading edge circuit transition is captured. This occurs in software.
摘要翻译：本发明提供了模拟信号转换。产生电路特性。电路特性被加载到存储器中。模拟电路行为。捕获非前沿电路转换。这发生在软件中。

5. 发明申请

US20060020443A1 Pulse waveform timing in EinsTLT templates 失效
标题翻译： EinsTLT模板中的脉冲波形定时
公开(公告)号：US20060020443A1
公开(公告)日：2006-01-26
申请号：US10897347
申请日：2004-07-22
申请人： Sang Lee , Vasant Rao , Jeffrey Soreff , James Warnock , David Winston
发明人： Sang Lee , Vasant Rao , Jeffrey Soreff , James Warnock , David Winston
IPC分类号： G06F9/455
CPC分类号： G06F17/5022
摘要： The present invention provides for simulating signal transitions. Circuit characteristics are generated. Circuit characteristics are loaded into memory. Circuit behaviour is simulated. A non-leading edge circuit transition is captured. This occurs in software.
摘要翻译：本发明提供了模拟信号转换。产生电路特性。电路特性被加载到存储器中。模拟电路行为。捕获非前沿电路转换。这发生在软件中。

6. 发明申请

US20070061647A1 Scan Chain Disable Function for Power Saving 失效
标题翻译：扫描链禁用功能用于省电
公开(公告)号：US20070061647A1
公开(公告)日：2007-03-15
申请号：US11552807
申请日：2006-10-25
申请人： Sang Dhong , Joel Silberman , Osamu Takahashi , James Warnock , Dieter Wendel
发明人： Sang Dhong , Joel Silberman , Osamu Takahashi , James Warnock , Dieter Wendel
IPC分类号： G01R31/28
CPC分类号： G06F1/3203 , G06F1/325
摘要： An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.
摘要翻译：提供了一种装置，方法和计算机程序产品，用于通过禁用扫描链来在处理器的功能模式期间节省能量。通过将逻辑门控插入到扫描链中，可以在处理器的功能模式期间禁用扫描链。在功能模式期间，扫描链中锁存位的扫描输出端口切换，这导致不必要的能量消耗。通过门控扫描控制信号和锁存位的扫描输出端口，可以断开锁存位之间的扫描链段。因此，扫描控制信号可以在功能模式下禁用扫描链。

7. 发明申请

US20060095802A1 Scan chain disable function for power saving 失效
标题翻译：扫描链禁用功能进行省电
公开(公告)号：US20060095802A1
公开(公告)日：2006-05-04
申请号：US10976259
申请日：2004-10-28
申请人： Sang Dhong , Joel Silberman , Osamu Takahashi , James Warnock , Dieter Wendel
发明人： Sang Dhong , Joel Silberman , Osamu Takahashi , James Warnock , Dieter Wendel
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/325
摘要： An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.
摘要翻译：提供了一种装置，方法和计算机程序产品，用于通过禁用扫描链来在处理器的功能模式期间节省能量。通过将逻辑门控插入到扫描链中，可以在处理器的功能模式期间禁用扫描链。在功能模式期间，扫描链中锁存位的扫描输出端口切换，这导致不必要的能量消耗。通过门控扫描控制信号和锁存位的扫描输出端口，可以断开锁存位之间的扫描链段。因此，扫描控制信号可以在功能模式下禁用扫描链。

8. 发明申请

US20050242439A1 METHOD AND STRUCTURE FOR CONNECTING GROUND/POWER NETWORKS TO PREVENT CHARGE DAMAGE IN SILICON ON INSULATOR 审中-公开
标题翻译：用于连接接地/电力网络以防止绝缘体上硅中的电荷损耗的方法和结构
公开(公告)号：US20050242439A1
公开(公告)日：2005-11-03
申请号：US10709325
申请日：2004-04-28
申请人： Kenneth DeVries , Jeffrey Gambino , Stephen Luce , James Warnock , Francis White
发明人： Kenneth DeVries , Jeffrey Gambino , Stephen Luce , James Warnock , Francis White
IPC分类号： H01L23/48 , H01L23/528
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A structure (and method) for an electronic chip, includes a first circuit design module having a first grid and a second circuit design module having a second grid. The first grid and the second grid are interconnected in a fabrication layer no later than a first metallization layer that accumulates a charge during a plasma process in the fabrication.
摘要翻译：一种用于电子芯片的结构（和方法）包括具有第一栅极的第一电路设计模块和具有第二栅极的第二电路设计模块。第一栅格和第二栅极在制造层中互连，不迟于在制造过程中等离子体处理期间积累电荷的第一金属化层。

9. 发明授权

US07340682B2 Method and system for controlling a complementary user interface on a display surface 失效
标题翻译：用于控制显示表面上的补充用户界面的方法和系统
公开(公告)号：US07340682B2
公开(公告)日：2008-03-04
申请号：US10435397
申请日：2003-05-09
申请人： D. David Nason , J. Scott Campbell , Phillip Brooks , Carson Kaan , Thomas C. O'Rourke , James Warnock , John Easton
发明人： D. David Nason , J. Scott Campbell , Phillip Brooks , Carson Kaan , Thomas C. O'Rourke , James Warnock , John Easton
IPC分类号： G06F3/00
CPC分类号： G09G5/14 , G06F9/451 , G09G1/16 , G09G1/165 , G09G2310/0232 , G09G2370/027
摘要： An alternate display content controller provides a technique for controlling a video display separately from and in addition to the content displayed on the operating system display surface. Where the display is a computer monitor, the alternate display content controller interacts with the computer utility operating system and hardware drivers to control allocation of display space and create and control one or more parallel graphical user interfaces adjacent the operating system desktop. An alternate display content controller may be incorporated in either hardware or software. As software, an alternate display content controller may be an application running on the computer operating system, or may include an operating system kernel of varying complexity ranging from dependent on the utility operating system for hardware system services to a parallel system independent of the utility operating system and capable of supporting dedicated applications. The alternate display content controller may also include content and operating software delivered over the internet or any other LAN. The alternate display content controller may also be included in a television decoder/settop box to permit two or more parallel graphical user interfaces to be displayed simultaneously.
摘要翻译：替代的显示内容控制器提供用于与显示在操作系统显示表面上的内容分离地以及除了显示在操作系统显示表面上的内容之外控制视频显示的技术在显示器是计算机监视器的情况下，备用显示内容控制器与计算机实用程序操作系统和硬件驱动程序交互以控制显示空间的分配，并创建和控制与操作系统桌面相邻的一个或多个并行图形用户界面。备用显示内容控制器可以并入硬件或软件中。作为软件，备用显示内容控制器可以是在计算机操作系统上运行的应用，或者可以包括不同复杂度的操作系统内核，从依赖于用于硬件系统服务的公用事业操作系统到独立于公用事业操作的并行系统系统并能够支持专用应用。备用显示内容控制器还可以包括通过互联网或任何其他LAN传递的内容和操作软件。备用显示内容控制器也可以包括在电视解码器/机顶盒中以允许同时显示两个或更多个并行图形用户界面。

10. 发明申请

US20060242506A1 HIGH-SPEED LEVEL SENSITIVE SCAN DESIGN TEST SCHEME WITH PIPELINED TEST CLOCKS 失效
标题翻译：高速水平敏感扫描设计测试方案与管道测试时钟
公开(公告)号：US20060242506A1
公开(公告)日：2006-10-26
申请号：US10908007
申请日：2005-04-25
申请人： James Warnock , William Huott
发明人： James Warnock , William Huott
IPC分类号： G01R31/28
CPC分类号： G01R31/318594
摘要： This invention describes a method of synchronizing test clocks in an LSSD system to achieve near simultaneous arrival of the clock signals at the inputs of all LSSD registers. The method relies on pipelining the latches to distribute the test clocks, where all pipeline latches are synchronized by the system clock. This enhancement improves the frequency at which the test clocks switch and improve the testing throughput by reducing testing time, resulting in significant reductions in testing hardware and overall time required for system test, without compromising any of the benefits associated with conventional LSSD techniques. The method further enhances the distribution of the test clock signals to points throughout the entire chip, with a distribution network that is tailored according to a desired LBIST speed.
摘要翻译：本发明描述了一种在LSSD系统中同步测试时钟的方法，以实现时钟信号在所有LSSD寄存器的输入端的近似同时到达。该方法依赖于流水线锁存器来分布测试时钟，其中所有流水线锁存器都通过系统时钟同步。该增强功能可以通过减少测试时间来提高测试时钟切换的频率，并提高测试吞吐量，从而大大降低了测试硬件和系统测试所需的总体时间，而不会影响与常规LSSD技术相关的任何优势。该方法进一步增强了测试时钟信号在整个芯片上的点的分布，其中分配网络根据期望的LBIST速度被定制。

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