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1. 发明授权

US07127560B2 Method of dynamically controlling cache size 有权
标题翻译：动态控制缓存大小的方法
公开(公告)号：US07127560B2
公开(公告)日：2006-10-24
申请号：US10605616
申请日：2003-10-14
申请人： Erwin B. Cohen , Thomas E. Cook , Ian R. Govett , Paul D. Kartschoke , Stephen V. Kosonocky , Peter A. Sandon , Keith R. Williams
发明人： Erwin B. Cohen , Thomas E. Cook , Ian R. Govett , Paul D. Kartschoke , Stephen V. Kosonocky , Peter A. Sandon , Keith R. Williams
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , G06F1/3225 , G06F12/0804 , G06F12/0864 , G06F2212/1028 , Y02D10/13 , Y02D10/14 , Y02D50/20 , Y10S707/99952
摘要： A power saving cache and a method of operating a power saving cache. The power saving cache includes circuitry to dynamically reduce the logical size of the cache in order to save power. Preferably, a method is used to determine optimal cache size for balancing power and performance, using a variety of combinable hardware and software techniques. Also, in a preferred embodiment, steps are used for maintaining coherency during cache resizing, including the handling of modified (“dirty”) data in the cache, and steps are provided for partitioning a cache in one of several way to provide an appropriate configuration and granularity when resizing.
摘要翻译：省电缓存和操作省电高速缓存的方法。省电高速缓存包括用于动态地减小高速缓存的逻辑大小以节省功率的电路。优选地，使用各种可组合的硬件和软件技术来使用一种方法来确定用于平衡功率和性能的最佳高速缓存大小。此外，在优选实施例中，步骤用于在高速缓存调整大小期间维持一致性，包括对高速缓存中的修改（“脏”）数据的处理，并且提供了用于以多种方式之一对高速缓存进行分区以提供适当配置的步骤调整大小时的粒度。

2. 发明申请

US20110048795A1 Electronic Package and Process 有权
标题翻译：电子封装和工艺
公开(公告)号：US20110048795A1
公开(公告)日：2011-03-03
申请号：US12552411
申请日：2009-09-02
申请人： Erwin B. Cohen , Martin P. Goetz , Jennifer V. Muncy
发明人： Erwin B. Cohen , Martin P. Goetz , Jennifer V. Muncy
IPC分类号： H05K7/20 , H05K13/00
CPC分类号： H05K7/20463
摘要： An electronic package has a cover or lid mounted onto a substrate to enclose an electronic device, and a liquid thermal interface material is subsequently inserted (through dispensing, injection molding or printing through apertures in the cover or lid) between the surface of the electronic device and the cover, and cured to a solid state.
摘要翻译：电子封装具有安装在基板上以封闭电子设备的盖或盖，并且随后将液体热界面材料（通过分配，注射成型或打印通过盖或盖中的孔）插入在电子设备的表面之间和盖子，并固化为固体状态。

3. 发明申请

US20080195986A1 POWER GRID TUNING FOR DC VOLTAGE EQUALIZATION 审中-公开
标题翻译：用于直流电压均衡的电网调谐
公开(公告)号：US20080195986A1
公开(公告)日：2008-08-14
申请号：US11674325
申请日：2007-02-13
申请人： Erwin B. Cohen , Mathew I. Ringler
发明人： Erwin B. Cohen , Mathew I. Ringler
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： A method for tuning a plurality of supply voltages across and integrated circuit (IC) package that supplies a number of voltage supply regions within an IC chip. The inventive method includes extracting a power draw for each voltage supply region and the region's functional circuit blocks to generate a current map, assigning C4 bumps and module pins, and designing an IC package layout to define a supply grid of metal conductive power distribution wiring, analyzing the IC package layout using an IR-drop application, creating an internal plane voltage map and an internal plane current map for each of the IC package voltage supply planes and identifying required via and plane current changes necessary to tune the IC package in accordance with plane voltage and plane current maps, and repeating the steps of assigning, analyzing and creating until the IR drops within the voltage supply regions of the IC package are thoroughly balanced.
摘要翻译：一种用于调整多个电源电压的方法以及提供IC芯片内的多个电压供应区域的集成电路（IC）封装。本发明的方法包括提取每个电压供应区域和区域的功能电路块的功率消耗，以产生电流映射，分配C4凸块和模块引脚，以及设计IC封装布局以定义金属导电配电布线的电网，使用IR-drop应用分析IC封装布局，为每个IC封装电压供应平面创建一个内部平面电压图和一个内部平面电流映射，并根据以下要求识别所需的通过和平面电流变化，以调整IC封装平面电压和平面电流映射，并且重复分配，分析和创建的步骤，直到IC封装的电压供应区域内的IR下降被彻底平衡为止。

4. 发明授权

US08756546B2 Elastic modulus mapping of a chip carrier in a flip chip package 失效
标题翻译：芯片载体在倒装芯片封装中的弹性模量映射
公开(公告)号：US08756546B2
公开(公告)日：2014-06-17
申请号：US13557386
申请日：2012-07-25
申请人： Erwin B. Cohen , Mark C. H. Lamorey , Marek A. Orlowski , Douglas O. Powell , David L. Questad , David B. Stone , Paul R. Walling
发明人： Erwin B. Cohen , Mark C. H. Lamorey , Marek A. Orlowski , Douglas O. Powell , David L. Questad , David B. Stone , Paul R. Walling
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.
摘要翻译：计算机实现的方法提供了倒装芯片封装的芯片载体的弹性模量图。将包括芯片载体的每个层的每个垂直对准子区域的电介质和导电设计元件的设计数据建模为弹簧以提供弹性模量图。确定芯片载体的子区域的弹性模量在芯片接合期间识别可能的机械故障位置并冷却倒装芯片封装。将焊料凸块修改为芯片载体可以减少施加到识别的可能的机械故障位置的应力。修改芯片载体设计以减少与识别出的可能的机械故障位置相关联的子区域的刚度，还可减少芯片连接和冷却的应力。

5. 发明授权

US07106110B2 Clock dithering system and method during frequency scaling 有权
标题翻译：时钟抖动系统和方法在频率缩放期间
公开(公告)号：US07106110B2
公开(公告)日：2006-09-12
申请号：US10710681
申请日：2004-07-28
申请人： Miles G. Canada , Erwin B. Cohen , Jay G. Heaslip , Cedric Lichtenau , Thomas Pflueger , Mathew I. Ringler
发明人： Miles G. Canada , Erwin B. Cohen , Jay G. Heaslip , Cedric Lichtenau , Thomas Pflueger , Mathew I. Ringler
IPC分类号： H03B19/00
CPC分类号： G06F1/08 , G06F1/324 , Y02D10/126
摘要： A system and method of shifting a clock frequency of an integrated circuit device from a first frequency to a second frequency, including alternating between the first frequency and the second frequency according to a dithering pattern, the alternating occurring for a predetermined number of cycles; and setting the clock frequency to the second frequency after the predetermined number of cycles.
摘要翻译：一种将集成电路装置的时钟频率从第一频率转换到第二频率的系统和方法，包括根据抖动模式在第一频率和第二频率之间交替，交替发生预定数量的周期; 并且在预定次数的周期之后将时钟频率设置为第二频率。

6. 发明申请

US20140033148A1 ELASTIC MODULUS MAPPING OF A CHIP CARRIER IN A FLIP CHIP PACKAGE 失效
标题翻译：芯片包装中的芯片载体的弹性模块映射
公开(公告)号：US20140033148A1
公开(公告)日：2014-01-30
申请号：US13557386
申请日：2012-07-25
申请人： Erwin B. Cohen , Mark C.H. Lamorey , Marek A. Orlowski , Douglas O. Powell , David L. Questad , David B. Stone , Paul R. Walling
发明人： Erwin B. Cohen , Mark C.H. Lamorey , Marek A. Orlowski , Douglas O. Powell , David L. Questad , David B. Stone , Paul R. Walling
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.
摘要翻译：计算机实现的方法提供了倒装芯片封装的芯片载体的弹性模量图。将包括芯片载体的每个层的每个垂直对准子区域的电介质和导电设计元件的设计数据建模为弹簧以提供弹性模量图。确定芯片载体的子区域的弹性模量在芯片接合期间识别可能的机械故障位置并冷却倒装芯片封装。将焊料凸块修改为芯片载体可以减少施加到识别的可能的机械故障位置的应力。修改芯片载体设计以减少与识别出的可能的机械故障位置相关联的子区域的刚度，还可减少芯片连接和冷却的应力。

7. 发明授权

US07759168B2 Electromagnetic interference shield for semiconductors using a continuous or near-continuous peripheral conducting seal and a conducting lid 失效
标题翻译：使用连续或近乎连续的外围导电密封和导电盖的半导体的电磁干扰屏蔽
公开(公告)号：US07759168B2
公开(公告)日：2010-07-20
申请号：US12119654
申请日：2008-05-13
申请人： J. Richard Behun , Erwin B. Cohen
发明人： J. Richard Behun , Erwin B. Cohen
IPC分类号： H01L21/52
CPC分类号： H01L23/552 , H01L23/04 , H01L23/10 , H01L24/16 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/16315 , H01L2924/166 , H01L2924/3025
摘要： A semiconductor package structure including a conductive adhesive material which is used to form an electromagnetic interference shield-forming Faraday cage. The Faraday cage incorporates a module lid as the top surface thereof, the conductive material as the sides and a laminate ground plane(s) or substrate as its bottom. Also disclosed is a method for fabricating the foregoing semiconductor package structure.
摘要翻译：一种半导体封装结构，包括用于形成电磁干扰屏蔽成形法拉第笼的导电粘合剂材料。法拉第笼包含模块盖作为其顶表面，导电材料作为侧面，并且层压接地平面或基底作为其底部。还公开了制造上述半导体封装结构的方法。

8. 发明申请

US20090283876A1 ELECTROMAGNETIC INTERFERENCE SHIELD FOR SEMICONDUCTORS USING A CONTINUOUS OR NEAR-CONTINUOUS PERIPHERAL CONDUCTING SEAL AND A CONDUCTING LID 失效
标题翻译：使用连续或近乎连续的外围导电密封和导电引线的半导体的电磁干扰屏蔽
公开(公告)号：US20090283876A1
公开(公告)日：2009-11-19
申请号：US12119654
申请日：2008-05-13
申请人： J. Richard Behun , Erwin B. Cohen
发明人： J. Richard Behun , Erwin B. Cohen
IPC分类号： H01L23/552 , H01L21/58
CPC分类号： H01L23/552 , H01L23/04 , H01L23/10 , H01L24/16 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/16315 , H01L2924/166 , H01L2924/3025
摘要： A semiconductor package structure including a conductive adhesive material which is used to form an electromagnetic interference shield-forming Faraday cage. The Faraday cage incorporates a module lid as the top surface thereof, the conductive material as the sides and a laminate ground plane(s) or substrate as its bottom. Also disclosed is a method for fabricating the foregoing semiconductor package structure.
摘要翻译：一种半导体封装结构，包括用于形成电磁干扰屏蔽成形法拉第笼的导电粘合剂材料。法拉第笼包含模块盖作为其顶表面，导电材料作为侧面，并且层压接地平面或基底作为其底部。还公开了制造上述半导体封装结构的方法。

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