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1. 发明授权

US07510634B1 Apparatus and methods for deposition and/or etch selectivity 有权
标题翻译：用于沉积和/或蚀刻选择性的装置和方法
公开(公告)号：US07510634B1
公开(公告)日：2009-03-31
申请号：US11558693
申请日：2006-11-10
申请人： Erich R. Klawuhn , Robert Rozbicki , Girish A. Dixit
发明人： Erich R. Klawuhn , Robert Rozbicki , Girish A. Dixit
IPC分类号： C23C14/35
CPC分类号： C23C14/046 , C23C14/3407 , C23C14/345 , C23C14/3492 , C23C14/35 , H01J37/32596 , H01J37/3405 , H01L21/2855 , H01L21/32131 , H01L21/76805 , H01L21/76814 , H01L21/76844 , H01L21/76868
摘要： Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage amount deposited in each trench is greater than the coverage amount deposited in each via.
摘要翻译：公开了用于在半导体晶片的通路和沟槽中实现蚀刻和/或沉积选择性的装置和方法实施例。也就是说，半导体晶片的每个通孔的底部的沉积覆盖不同于这种晶片的每个沟槽的底部的覆盖。选择性可以被配置为导致每个通孔中的穿孔而不损坏每个沟槽等的底部处的电介质材料。在这种配置中，沉积在每个沟槽中的覆盖率大于沉积在每个通孔中的覆盖量。

2. 发明授权

US08858763B1 Apparatus and methods for deposition and/or etch selectivity 有权
标题翻译：用于沉积和/或蚀刻选择性的装置和方法
公开(公告)号：US08858763B1
公开(公告)日：2014-10-14
申请号：US12391719
申请日：2009-02-24
申请人： Erich R. Klawuhn , Robert Rozbicki , Girish A. Dixit
发明人： Erich R. Klawuhn , Robert Rozbicki , Girish A. Dixit
IPC分类号： C23C14/34
CPC分类号： C23C14/046 , C23C14/3407 , C23C14/345 , C23C14/3492 , C23C14/35 , H01J37/32596 , H01J37/3405 , H01L21/2855 , H01L21/32131 , H01L21/76805 , H01L21/76814 , H01L21/76844 , H01L21/76868
摘要： Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage amount deposited in each trench is greater than the coverage amount deposited in each via.
摘要翻译：公开了用于在半导体晶片的通路和沟槽中实现蚀刻和/或沉积选择性的装置和方法实施例。也就是说，半导体晶片的每个通孔的底部的沉积覆盖不同于这种晶片的每个沟槽的底部的覆盖。选择性可以被配置为导致每个通孔中的穿孔而不损坏每个沟槽等的底部处的电介质材料。在这种配置中，沉积在每个沟槽中的覆盖率大于沉积在每个通孔中的覆盖量。

3. 发明授权

US08749868B2 Electrochromic devices 有权
公开(公告)号：US08749868B2
公开(公告)日：2014-06-10
申请号：US13610684
申请日：2012-09-11
申请人： Zhongchun Wang , Anshu Pradhan , Robert Rozbicki
发明人： Zhongchun Wang , Anshu Pradhan , Robert Rozbicki
IPC分类号： G02F1/15
CPC分类号： G02F1/155 , C23C14/083 , C23C14/34 , C23C14/5806 , G02F1/1508 , G02F1/1523 , G02F1/153 , G02F2001/1555 , H01J37/3426
摘要： Conventional electrochromic devices frequently suffer from poor reliability and poor performance. Improvements are made using entirely solid and inorganic materials. Electrochromic devices are fabricated by forming an ion conducting electronically insulating interfacial region that serves as an IC layer. In some methods, the interfacial region is formed after formation of an electrochromic and a counter electrode layer. The interfacial region contains an ion conducting electronically insulating material along with components of the electrochromic and/or the counter electrode layer. Materials and microstructure of the electrochromic devices provide improvements in performance and reliability over conventional devices.

4. 发明授权

US07781327B1 Resputtering process for eliminating dielectric damage 有权
标题翻译：用于消除电介质损伤的再溅射过程
公开(公告)号：US07781327B1
公开(公告)日：2010-08-24
申请号：US11588586
申请日：2006-10-26
申请人： Sridhar Kailasam , Robert Rozbicki , Chentao Yu , Douglas Hayden
发明人： Sridhar Kailasam , Robert Rozbicki , Chentao Yu , Douglas Hayden
IPC分类号： H01L21/4763
CPC分类号： H01L21/2855 , H01L21/76805 , H01L21/76814 , H01L21/76843 , H01L21/76844 , H01L21/76865
摘要： Methods of resputtering material from the wafer surface include at least one operation of resputtering material under a pressure of at least 10 mTorr. The methods can be used in conjunction with an iPVD apparatus, such as hollow cathode magnetron (HCM) or planar magnetron. The resputtered material may be a diffusion barrier material or a conductive layer material. The methods provide process conditions which minimize the damage to the dielectric layer during resputtering. The methods allow considerable etching of the diffusion barrier material at the via bottom, while not damaging exposed dielectric elsewhere on the wafer. Specifically, they provide a solution for the dielectric microtrenching problem occurring during conventional resputter process. Furthermore, the methods increase the etch rate to deposition rate ratio (E/D) and improve the etch back nonuniformity (EBNU) of resputter process. In general, the methods provide IC devices with higher reliability and decrease wafer manufacturing costs.
摘要翻译：从晶片表面重新溅射材料的方法包括在至少10mTorr的压力下重新溅射材料的至少一种操作。该方法可以与iPVD装置结合使用，例如空心阴极磁控管（HCM）或平面磁控管。所述重排材料可以是扩散阻挡材料或导电层材料。该方法提供了在再溅射期间最小化对电介质层的损伤的工艺条件。这些方法允许在通孔底部对扩散阻挡材料进行相当大的蚀刻，同时不损坏晶片上其他地方的暴露的电介质。具体地说，它们提供了在常规的再溅射过程中发生的介电微切削问题的解决方案。此外，这些方法将蚀刻速率提高到沉积速率比（E / D），并提高了回溅过程的回蚀不均匀性（EBNU）。通常，这些方法为IC器件提供了更高的可靠性并降低了晶片制造成本。

5. 发明授权

US07732314B1 Method for depositing a diffusion barrier for copper interconnect applications 有权
标题翻译：用于沉积铜互连应用的扩散阻挡层的方法
公开(公告)号：US07732314B1
公开(公告)日：2010-06-08
申请号：US11714465
申请日：2007-03-05
申请人： Michal Danek , Robert Rozbicki
发明人： Michal Danek , Robert Rozbicki
IPC分类号： H01L21/20
CPC分类号： H01L21/76814 , H01L21/2855 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76865
摘要： Methods for forming a metal diffusion barrier on an integrated circuit include at least four operations. The first operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The third operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage especially over the bottoms of unlanded vias. The forth operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects. In addition, techniques to protect the bottoms of the unlanded vias are described.
摘要翻译：在集成电路上形成金属扩散阻挡层的方法包括至少四个操作。第一个操作通过PVD，ALD或CVD沉积阻挡材料以提供一些最小的覆盖。第二操作沉积另外的阻挡材料，同时蚀刻在第一操作中沉积的阻挡材料的一部分。第三个操作通过PVD，ALD或CVD沉积阻挡材料，以提供一些最小的覆盖范围，特别是在非通孔的底部。第四操作沉积金属导电层。使用受控蚀刻来选择性地从通孔底部去除屏障材料，完全或部分地去除，从而降低随后形成的金属互连的电阻。此外，描述了保护未经过过孔的底部的技术。

6. 发明授权

US08243357B2 Fabrication of low defectivity electrochromic devices 有权
标题翻译：低缺陷电致变色器件的制造
公开(公告)号：US08243357B2
公开(公告)日：2012-08-14
申请号：US13105776
申请日：2011-05-11
申请人： Mark Kozlowski , Eric Kurman , Zhongchun Wang , Mike Scobey , Jeremy Dixon , Anshu Pradhan , Robert Rozbicki
发明人： Mark Kozlowski , Eric Kurman , Zhongchun Wang , Mike Scobey , Jeremy Dixon , Anshu Pradhan , Robert Rozbicki
IPC分类号： G02F1/153 , G02F1/15
CPC分类号： G02F1/1523 , B05D5/06 , B23K20/10 , C03C17/3417 , C03C2217/94 , C23C10/28 , C23C14/021 , C23C14/022 , C23C14/024 , C23C14/046 , C23C14/08 , C23C14/083 , C23C14/085 , C23C14/086 , C23C14/14 , C23C14/185 , C23C14/3407 , C23C14/568 , C23C14/58 , C23C14/5806 , C23C14/5853 , G02F1/15 , G02F1/153 , G02F1/1533 , G02F1/155
摘要： Prior electrochromic devices frequently suffer from high levels of defectivity. The defects may be manifest as pin holes or spots where the electrochromic transition is impaired. This is unacceptable for many applications such as electrochromic architectural glass. Improved electrochromic devices with low defectivity can be fabricated by depositing certain layered components of the electrochromic device in a single integrated deposition system. While these layers are being deposited and/or treated on a substrate, for example a glass window, the substrate never leaves a controlled ambient environment, for example a low pressure controlled atmosphere having very low levels of particles. These layers may be deposited using physical vapor deposition.
摘要翻译：先前的电致变色器件经常遭受高水平的缺陷。缺陷可能表现为电致变色转变受损的针孔或斑点。这对于许多应用如电致变色建筑玻璃是不可接受的。具有低缺陷性的改进的电致变色器件可以通过将电致变色器件的某些分层部件沉积在单个集成沉积系统中来制造。虽然这些层被沉积和/或在衬底（例如玻璃窗）上被沉积和/或处理，但是衬底从不离开受控的环境环境，例如具有非常低水平粒子的低压控制气氛。可以使用物理气相沉积来沉积这些层。

7. 发明申请

US20110266137A1 ELECTROCHROMIC DEVICES 有权
公开(公告)号：US20110266137A1
公开(公告)日：2011-11-03
申请号：US12814277
申请日：2010-06-11
申请人： Zhongchun Wang , Anshu Pradhan , Robert Rozbicki
发明人： Zhongchun Wang , Anshu Pradhan , Robert Rozbicki
IPC分类号： C23C14/34
CPC分类号： C23C14/083 , G02F1/1523 , G02F1/1525
摘要： Conventional electrochromic devices frequently suffer from poor reliability and poor performance. Improvements are made using entirely solid and inorganic materials. Electrochromic devices are fabricated by forming an ion conducting electronically-insulating interfacial region that serves as an IC layer. In some methods, the interfacial region is formed after formation of an electrochromic and a counter electrode layer. The interfacial region contains an ion conducting electronically-insulating material along with components of the electrochromic and/or the counter electrode layer. Materials and microstructure of the electrochromic devices provide improvements in performance and reliability over conventional devices.

8. 发明申请

US20110211247A1 FABRICATION OF LOW DEFECTIVITY ELECTROCHROMIC DEVICES 有权
标题翻译：低缺陷电致发光器件的制造
公开(公告)号：US20110211247A1
公开(公告)日：2011-09-01
申请号：US13105776
申请日：2011-05-11
申请人： Mark Kozlowski , Eric Kurman , Zhongchun Wang , Mike Scobey , Jeremy Dixon , Anshu Pradhan , Robert Rozbicki
发明人： Mark Kozlowski , Eric Kurman , Zhongchun Wang , Mike Scobey , Jeremy Dixon , Anshu Pradhan , Robert Rozbicki
IPC分类号： G02F1/155
CPC分类号： G02F1/1523 , B05D5/06 , B23K20/10 , C03C17/3417 , C03C2217/94 , C23C10/28 , C23C14/021 , C23C14/022 , C23C14/024 , C23C14/046 , C23C14/08 , C23C14/083 , C23C14/085 , C23C14/086 , C23C14/14 , C23C14/185 , C23C14/3407 , C23C14/568 , C23C14/58 , C23C14/5806 , C23C14/5853 , G02F1/15 , G02F1/153 , G02F1/1533 , G02F1/155
摘要： Prior electrochromic devices frequently suffer from high levels of defectivity. The defects may be manifest as pin holes or spots where the electrochromic transition is impaired. This is unacceptable for many applications such as electrochromic architectural glass. Improved electrochromic devices with low defectivity can be fabricated by depositing certain layered components of the electrochromic device in a single integrated deposition system. While these layers are being deposited and/or treated on a substrate, for example a glass window, the substrate never leaves a controlled ambient environment, for example a low pressure controlled atmosphere having very low levels of particles. These layers may be deposited using physical vapor deposition.
摘要翻译：先前的电致变色器件经常遭受高水平的缺陷。缺陷可能表现为电致变色转变受损的针孔或斑点。这对于许多应用如电致变色建筑玻璃是不可接受的。具有低缺陷性的改进的电致变色器件可以通过将电致变色器件的某些分层部件沉积在单个集成沉积系统中来制造。虽然这些层被沉积和/或在衬底（例如玻璃窗）上被沉积和/或处理，但是衬底从不离开受控的环境环境，例如具有非常低水平粒子的低压控制气氛。可以使用物理气相沉积来沉积这些层。

9. 发明授权

US07186648B1 Barrier first method for single damascene trench applications 有权
标题翻译：单一大马士革沟槽应用的屏障第一种方法
公开(公告)号：US07186648B1
公开(公告)日：2007-03-06
申请号：US10804353
申请日：2004-03-18
申请人： Robert Rozbicki , Michal Danek
发明人： Robert Rozbicki , Michal Danek
IPC分类号： H01L21/44
CPC分类号： H01L21/76814 , H01L21/2855 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76865
摘要： Methods for forming a diffusion barrier on low aspect features of an integrated circuit include at least three operations. The first operation deposits a barrier material and simultaneously etches a portion of an underlying metal at the bottoms of recessed features of the integrated circuit. The second operation deposits barrier material to provide some minimal coverage over the bottoms of the recessed features. The third operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of the recessed features, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.
摘要翻译：在集成电路的低方面特征上形成扩散阻挡层的方法包括至少三个操作。第一操作沉积阻挡材料并且同时在集成电路的凹陷特征的底部蚀刻下面的金属的一部分。第二操作沉积阻挡材料以在凹陷特征的底部提供一些最小的覆盖。第三操作沉积金属导电层。使用受控蚀刻来完全或部分地从凹陷特征的底部选择性地去除阻挡材料，从而降低随后形成的金属互连的电阻。

10. 发明授权

US06764940B1 Method for depositing a diffusion barrier for copper interconnect applications 有权
标题翻译：用于沉积铜互连应用的扩散阻挡层的方法
公开(公告)号：US06764940B1
公开(公告)日：2004-07-20
申请号：US10412562
申请日：2003-04-11
申请人： Robert Rozbicki , Michal Danek
发明人： Robert Rozbicki , Michal Danek
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01J37/32082 , H01L21/02043 , H01L21/76805 , H01L21/76807 , H01L21/76844 , H01L21/76846 , H01L21/7685 , H01L21/76862 , H01L21/76865 , H01L21/76883
摘要： Methods for forming a metal diffusion barrier on an integrated circuit include at least four operations. The first operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The third operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage especially over the bottoms of unlanded vias. The forth operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects. In addition, techniques to protect the bottoms of the unlanded vias are described.
摘要翻译：在集成电路上形成金属扩散阻挡层的方法包括至少四个操作。第一个操作通过PVD，ALD或CVD沉积阻挡材料以提供一些最小的覆盖。第二操作沉积另外的阻挡材料，同时蚀刻在第一操作中沉积的阻挡材料的一部分。第三个操作通过PVD，ALD或CVD沉积阻挡材料，以提供一些最小的覆盖范围，特别是在非通孔的底部。第四操作沉积金属导电层。使用受控蚀刻来选择性地从通孔底部去除屏障材料，完全或部分地去除，从而降低随后形成的金属互连的电阻。此外，描述了保护未经过过孔的底部的技术。

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