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1. 发明授权

US07984281B2 Shared interrupt controller for a multi-threaded processor 有权
标题翻译：用于多线程处理器的共享中断控制器
公开(公告)号：US07984281B2
公开(公告)日：2011-07-19
申请号：US11954615
申请日：2007-12-12
申请人： Erich James Plondke , Lucian Codrescu , Muhammad Ahmed , William Anderson , Suresh K. Venkumahanti
发明人： Erich James Plondke , Lucian Codrescu , Muhammad Ahmed , William Anderson , Suresh K. Venkumahanti
IPC分类号： G06F9/00
CPC分类号： G06F9/4812 , G06F9/30123 , G06F9/3013 , G06F9/3851
摘要： A multi-threaded processor is disclosed that includes a sequencer adapted to provide instructions associated with one or more threads of a multi-threaded processor. The sequencer includes an interrupt controller adapted to receive one or more interrupts and to selectively allow a first thread of the one or more threads to service at least one interrupt. The interrupt controller includes logic to preclude a second thread of the one or more threads from responding to the at least one interrupt.
摘要翻译：公开了一种多线程处理器，其包括适于提供与多线程处理器的一个或多个线程相关联的指令的定序器。定序器包括适于接收一个或多个中断并且选择性地允许一个或多个线程的第一线程服务于至少一个中断的中断控制器。所述中断控制器包括排除所述一个或多个线程的第二线程以响应所述至少一个中断的逻辑。

2. 发明申请

US20060242384A1 Register files for a digital signal processor operating in an interleaved multi-threaded environment 有权
标题翻译：为交错多线程环境中的数字信号处理器注册文件
公开(公告)号：US20060242384A1
公开(公告)日：2006-10-26
申请号：US11115916
申请日：2005-04-26
申请人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William Anderson
发明人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William Anderson
IPC分类号： G06F15/00
CPC分类号： G06F9/30149 , G06F9/3012 , G06F9/3851 , G06F9/3885
摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.
摘要翻译：公开了处理器设备，并且包括响应于存储器的存储器和定序器。定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。此外，多个寄存器文件中的每一个包括多个数据读取端口，并且多个寄存器堆栈中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。

3. 发明申请

US20060230253A1 Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment 审中-公开
标题翻译：用于在交错多线程环境中工作的数字信号处理器的统一非分区寄存器文件
公开(公告)号：US20060230253A1
公开(公告)日：2006-10-12
申请号：US11103744
申请日：2005-04-11
申请人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , William Anderson , Taylor Simpson
发明人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , William Anderson , Taylor Simpson
IPC分类号： G06F15/00
CPC分类号： H04M1/72522 , G06F9/3012 , G06F9/3885 , H04M1/2535 , H04M2250/02
摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit responsive to the sequencer, a third instruction execution unit responsive to the sequencer, and a fourth instruction execution unit responsive to the sequencer. Further, the processor device includes a plurality of register files and each of the plurality of register files includes a plurality of registers. The plurality of register files are coupled to the sequencer and coupled to the first instruction execution unit, the second instruction execution unit, the third instruction execution unit, and the fourth instruction execution unit.
摘要翻译：公开了处理器设备，并且包括响应于存储器的存储器和定序器。音序器可以支持非常长的指令字（VLIW）指令和超标量指令。处理器装置还包括响应于定序器的第一指令执行单元，响应于定序器的第二指令执行单元，响应于定序器的第三指令执行单元，以及响应于定序器的第四指令执行单元。此外，处理器装置包括多个寄存器文件，并且多个寄存器文件中的每一个包括多个寄存器。多个寄存器文件耦合到定序器并耦合到第一指令执行单元，第二指令执行单元，第三指令执行单元和第四指令执行单元。

4. 发明申请

US20060218559A1 Method and system for variable thread allocation and switching in a multithreaded processor 有权
标题翻译：多线程处理器中可变线程分配和切换的方法和系统
公开(公告)号：US20060218559A1
公开(公告)日：2006-09-28
申请号：US11089474
申请日：2005-03-23
申请人： Muhammad Ahmed , Sujat Jamil , Erich Plondke , Lucian Codrescu , William Anderson
发明人： Muhammad Ahmed , Sujat Jamil , Erich Plondke , Lucian Codrescu , William Anderson
IPC分类号： G06F9/46
CPC分类号： G06F9/3851
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method further switches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.
摘要翻译：用于在通信（例如，CDMA）系统中处理传输的技术。所公开的主题的一个方面包括用于在多线程处理器上处理指令的方法。多线程处理器经由多个处理器管线处理多个线程。该方法包括确定多线程处理器工作的工作频率F的步骤。然后，该方法确定用于触发多个活动线程之间的处理切换的可变线程切换超时状态。可变线程切换超时状态改变，使得多个活动线程中的每一个以所分配的频率部分F的频率运行。活动线程运行的分配部分至少部分地被确定，以便优化操作多线程处理器。在发生可变线程切换超时状态时，该方法还将处理从主动线程中的第一个切换到下一个活动线程。

5. 发明申请

US20060212681A1 Processor and method of grouping and executing dependent instructions in a packet 有权
公开(公告)号：US20060212681A1
公开(公告)日：2006-09-21
申请号：US11086475
申请日：2005-03-21
申请人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , Sujat Jamil , William Anderson
发明人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , Sujat Jamil , William Anderson
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/3851 , G06F9/3853
摘要： An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a first execution unit for execution and generating a first result, steering a second instruction of the instruction packet to a second execution unit for execution using the first result and generating a second result, and storing the second result.

6. 发明申请

US20060230257A1 System and method of using a predicate value to access a register file 审中-公开
标题翻译：使用谓词值访问寄存器文件的系统和方法
公开(公告)号：US20060230257A1
公开(公告)日：2006-10-12
申请号：US11104163
申请日：2005-04-11
申请人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William Anderson
发明人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William Anderson
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/3885
摘要： A processor device is disclosed and includes a memory unit and at least one interleaved multi-threading instruction pipeline. The interleaved multi-threading instruction pipeline utilizes a number of clock cycles that is less than an instruction issue rate for each of a plurality of program threads that are stored within the memory unit. The memory unit includes six instruction caches. Further, the processor device includes six register files and each of the six register files is associated with one of the six instruction caches. Each of the plurality of program threads is associated with one of the six register files. Further, each of the six program threads includes a plurality of instructions and each of the plurality of instructions is stored within one of the six instruction caches of the memory.
摘要翻译：公开了处理器设备，并且包括存储器单元和至少一个交错多线程指令流水线。交错多线程指令流水线利用小于存储在存储器单元内的多个程序线程中的每一个的指令发布速率的多个时钟周期。存储单元包括六个指令高速缓存。此外，处理器设备包括六个寄存器文件，六个寄存器文件中的每一个与六个指令高速缓存中的一个相关联。多个程序线程中的每一个与六个寄存器文件中的一个相关联。此外，六个程序线程中的每一个包括多个指令，并且多个指令中的每一个被存储在存储器的六个指令高速缓存之一中。

7. 发明申请

US20080091867A1 Shared interrupt controller for a multi-threaded processor 有权
标题翻译：用于多线程处理器的共享中断控制器
公开(公告)号：US20080091867A1
公开(公告)日：2008-04-17
申请号：US11954615
申请日：2007-12-12
申请人： Erich Plondke , Lucian Codrescu , Muhammad Ahmed , William Anderson , Suresh Venkumahanti
发明人： Erich Plondke , Lucian Codrescu , Muhammad Ahmed , William Anderson , Suresh Venkumahanti
IPC分类号： G06F9/26
CPC分类号： G06F9/4812 , G06F9/30123 , G06F9/3013 , G06F9/3851
摘要： A multi-threaded processor is disclosed that includes a sequencer adapted to provide instructions associated with one or more threads of a multi-threaded processor. The sequencer includes an interrupt controller adapted to receive one or more interrupts and to selectively allow a first thread of the one or more threads to service at least one interrupt. The interrupt controller includes logic to preclude a second thread of the one or more threads from responding to the at least one interrupt.
摘要翻译：公开了一种多线程处理器，其包括适于提供与多线程处理器的一个或多个线程相关联的指令的定序器。定序器包括适于接收一个或多个中断并且选择性地允许一个或多个线程的第一线程服务于至少一个中断的中断控制器。所述中断控制器包括排除所述一个或多个线程的第二线程以响应所述至少一个中断的逻辑。

8. 发明申请

US20070094478A1 Pointer computation method and system for a scalable, programmable circular buffer 审中-公开
标题翻译：指针计算方法和系统，用于可扩展的可编程循环缓冲区
公开(公告)号：US20070094478A1
公开(公告)日：2007-04-26
申请号：US11255434
申请日：2005-10-20
申请人： Erich Plondke , Lucian Codrescu , Muhammad Ahmed , Mao Zeng , Sujat Jamil , William Anderson
发明人： Erich Plondke , Lucian Codrescu , Muhammad Ahmed , Mao Zeng , Sujat Jamil , William Anderson
IPC分类号： G06F12/00
CPC分类号： G06F5/10 , G06F9/3552 , G06F9/3851 , G06F2205/106
摘要： Techniques for processing digital signals for a variety of applications, including in a communications (e.g., CDMA) system. A pointer location within a circular buffer is determined by establishing a length of the circular buffer, a start address that is aligned to a power of 2, and an end address located distant from the start address by the length and less than a power of 2 greater than the length. The method and system determine a current pointer location for an address within the circular buffer, a stride value of bits between the start address and the end address, a new pointer location within the circular buffer that is shifted from the current pointer location by the number of bits of the stride value. An adjusted pointer location is within the circular buffer by an arithmetic operation of the new pointer location with the length.
摘要翻译：用于处理包括在通信（例如CDMA）系统中的各种应用的数字信号的技术。循环缓冲器中的指针位置通过建立循环缓冲器的长度，与2的幂对齐的起始地址和远离起始地址长度并小于2的幂的结束地址来确定大于长度。该方法和系统确定循环缓冲器中的地址的当前指针位置，起始地址和结束地址之间的位的步幅值，循环缓冲器内的新指针位置，其从当前指针位置移位数字的步幅值。通过具有长度的新指针位置的算术运算，调整的指针位置在循环缓冲器内。

9. 发明申请

US20060242645A1 System and method of executing program threads in a multi-threaded processor 有权
标题翻译：在多线程处理器中执行程序线程的系统和方法
公开(公告)号：US20060242645A1
公开(公告)日：2006-10-26
申请号：US11115917
申请日：2005-04-26
申请人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , William Anderson
发明人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , William Anderson
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3853
摘要： A multithreaded processor device is disclosed and includes a first program thread and second program thread. The second program thread is execution linked to the first program thread in a lock step manner. As such, when the first program thread experiences a stall event, the second program thread is instructed to perform a no operation instruction in order to keep the second program thread execution linked to the first program thread. Also, the second program thread performs a no operation instruction during each clock cycle that the first program thread is stalled due to the stall event. When the first program thread performs a first successful operation after the stall event, the second program thread restarts normal execution.
摘要翻译：公开了一种多线程处理器设备，并且包括第一程序线程和第二程序线程。第二个程序线程以锁定步骤的方式执行链接到第一个程序线程。这样，当第一程序线程经历停顿事件时，指示第二程序线程执行无操作指令，以便使第二程序线程执行与第一程序线程相关联。此外，第二程序线程在每个时钟周期期间执行无操作指令，由于失速事件使第一程序线程停滞。当第一程序线程在停止事件之后执行第一次成功操作时，第二程序线程重新启动正常执行。

10. 发明申请

US20060218373A1 Processor and method of indirect register read and write operations 有权
标题翻译：间接寄存器读写操作的处理器和方法
公开(公告)号：US20060218373A1
公开(公告)日：2006-09-28
申请号：US11089619
申请日：2005-03-24
申请人： Erich Plondke , Lucian Codrescu , Muhammad Ahmed , William Anderson
发明人： Erich Plondke , Lucian Codrescu , Muhammad Ahmed , William Anderson
IPC分类号： G06F9/34
CPC分类号： G06F9/35 , G06F9/3851 , G06F9/3853
摘要： A processor is operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the first register-out value and obtaining a second register-out value, and storing the second register-out value into a third register based on the program instruction. The processor is further operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the program instruction and obtaining a second register-out value, and storing the first register-out value into a third register based on the second register-out value.
摘要翻译：处理器可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于第一寄存器输出值访问第二寄存器并获得第二寄存器值，以及基于所述程序指令将所述第二寄存器值存储到第三寄存器中。处理器还可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于所述程序指令访问第二寄存器并获得第二寄存器值，以及存储基于第二寄存器值将第一寄存器值输入到第三寄存器中。

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