专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07787471B2 Field processor for a network device 失效
标题翻译：网络设备的现场处理器
公开(公告)号：US07787471B2
公开(公告)日：2010-08-31
申请号：US10985033
申请日：2004-11-10
申请人： Eric A. Baden , Mohan Kalkunte , John J. Dull , Venkateshwar Buduma
发明人： Eric A. Baden , Mohan Kalkunte , John J. Dull , Venkateshwar Buduma
IPC分类号： H04L12/54
CPC分类号： H04L47/10 , H04L45/7453 , H04L47/20 , H04L47/2408 , H04L47/2441 , H04L47/2458 , H04L47/32 , H04L69/22
摘要： A method of handling a datagram in a network device is disclosed. The steps include receiving a datagram, with the datagram having multiple field values, at a port of a network device, parsing the received datagram to obtain the field values, applying the parsed field values to a Ternary Content Addressable Memory (TCAM), determining matches between the parsed field values and predetermined criteria in the TCAM, indexing into a policy table based on the determined matches to obtain an action entry and taking an action based on the obtained action entry.
摘要翻译：公开了一种在网络设备中处理数据报的方法。这些步骤包括在网络设备的端口处接收具有多个字段值的数据报的数据报，解析接收到的数据报以获得字段值，将解析的字段值应用于三元内容可寻址存储器（TCAM），确定匹配在解析的字段值和TCAM中的预定标准之间，基于所确定的匹配来索引到策略表中，以获得动作条目并基于获得的动作条目采取动作。

2. 发明授权

US07986616B2 System and method for maintaining a layer 2 modification buffer 有权
标题翻译：用于维护第2层修改缓冲区的系统和方法
公开(公告)号：US07986616B2
公开(公告)日：2011-07-26
申请号：US12535739
申请日：2009-08-05
申请人： Michael J. Bowes , Eric A. Baden , John J. Dull , Curt McDowell
发明人： Michael J. Bowes , Eric A. Baden , John J. Dull , Curt McDowell
IPC分类号： H04L12/26 , G06F15/177 , G06F7/00
CPC分类号： H04L49/3072 , H04L49/201 , H04L49/3009 , H04L49/351 , H04L49/508
摘要： A network device for processing packets. The network devices includes a ingress module for performing lookups for layer 2 switching and performing operations for maintaining a layer 2 table. When the ingress module updates the layer 2 table, the ingress module records the operation performed on the layer 2 table in a modification buffer. Entries are added to the modification buffer when the layer 2 table is modified and in the order in which the layer 2 table was modified. The network device thus enables reconstruction of the layer 2 table by performing the operations in the modification buffer.
摘要翻译：用于处理数据包的网络设备。网络设备包括用于执行用于层2切换的查找并执行维护层2表的操作的入口模块。当入口模块更新第2层表时，入口模块将修改缓冲区中的第2层表上执行的操作记录下来。当修改第2层表时，按照修改第2层表的顺序将条目添加到修改缓冲区。因此，通过执行修改缓冲器中的操作，网络设备能够重构第2层。

3. 发明授权

US08706736B2 Extended width entries for hash tables 失效
标题翻译：散列表的扩展宽度条目
公开(公告)号：US08706736B2
公开(公告)日：2014-04-22
申请号：US13249793
申请日：2011-09-30
申请人： Brandon C. Smith , John J. Dull , Vamsi Tatapudi
发明人： Brandon C. Smith , John J. Dull , Vamsi Tatapudi
IPC分类号： G06F17/30
CPC分类号： G06F17/30949 , H04L45/7453
摘要： A hash table supports extended entries. The extended entries permit a base entry to extend its associated data into one or more neighboring entries. Extended entries thereby provide a mechanism through which a hash table entry may store additional data compared to a base entry. Extended entries may coexist with base entries in the hash table. The hash table thereby provides the flexibility to adapt dynamically to meet system requirements and to balance the needs of additional data storage by blending the number of extended entries (that each store more data than a base entry) and the number of base entries (each storing less data than an extended entry).
摘要翻译：哈希表支持扩展条目。扩展条目允许基本条目将其相关联的数据扩展到一个或多个相邻条目。因此，扩展条目提供了一种机制，散列表条目可以与基本条目相比较地存储附加数据。扩展条目可能与哈希表中的基本条目共存。因此，散列表提供了灵活性，以动态地适应以满足系统需求，并且通过混合扩展条目的数量（每个存储比基本条目更多的数据）和基本条目的数量（每个存储少于扩展条目的数据）。

4. 发明申请

US20140079073A1 Dynamic Clock Gating in a Network Device 有权
标题翻译：网络设备中的动态时钟门控
公开(公告)号：US20140079073A1
公开(公告)日：2014-03-20
申请号：US13618411
申请日：2012-09-14
申请人： Sachin P. Kadu , John J. Dull
发明人： Sachin P. Kadu , John J. Dull
IPC分类号： H04L12/56
CPC分类号： H04L49/00 , H04L49/1546
摘要： A switch device that includes a switch pipeline stage to process packet data may selectively clock multiple pipeline sub-stages within the switch pipeline stage. The switch device may provide a first clock to processing logic of a first sub-stage independently of providing a second clock to a processing logic of second sub-stage within the switch pipeline stage. Clocking logic associated with a current switch pipeline stage may receive an event indication, such as an event indication from a previous pipeline stage responsive to processing of packet data by the previous pipeline stage. In response, the clocking logic associated with the current switch pipeline stage may determine a clocking time to issue a clock to a selected pipeline sub-stage in the current switch pipeline stage. The clocking logic may also issue the clock to the selected pipeline sub-stage at the clocking time.
摘要翻译：包括用于处理分组数据的交换流水线级的交换机设备可以选择性地在该交换机流水线级内更新多个流水线子阶段。交换设备可以提供第一时钟来处理第一子阶段的逻辑，而不管将第二时钟提供给交换机流水线阶段内的第二子阶段的处理逻辑。与当前交换流水线级相关联的时钟逻辑可以响应于先前流水线级对分组数据的处理来接收诸如来自先前流水线级的事件指示的事件指示。作为响应，与当前交换流水线级相关联的时钟逻辑可以确定在当前交换流水线级中向所选流水线子级发出时钟的时钟时间。时钟逻辑还可以在时钟时间向所选流水线子级发出时钟。

5. 发明授权

US08873576B2 Dynamic clock gating in a network device 有权
标题翻译：网络设备中的动态时钟门控
公开(公告)号：US08873576B2
公开(公告)日：2014-10-28
申请号：US13618411
申请日：2012-09-14
申请人： Sachin P. Kadu , John J. Dull
发明人： Sachin P. Kadu , John J. Dull
IPC分类号： H04L12/66
CPC分类号： H04L49/00 , H04L49/1546
摘要： A switch device that includes a switch pipeline stage to process packet data may selectively clock multiple pipeline sub-stages within the switch pipeline stage. The switch device may provide a first clock to processing logic of a first sub-stage independently of providing a second clock to a processing logic of second sub-stage within the switch pipeline stage. Clocking logic associated with a current switch pipeline stage may receive an event indication, such as an event indication from a previous pipeline stage responsive to processing of packet data by the previous pipeline stage. In response, the clocking logic associated with the current switch pipeline stage may determine a clocking time to issue a clock to a selected pipeline sub-stage in the current switch pipeline stage. The clocking logic may also issue the clock to the selected pipeline sub-stage at the clocking time.
摘要翻译：包括用于处理分组数据的交换流水线级的交换机设备可以选择性地在该交换机流水线级内更新多个流水线子阶段。交换设备可以提供第一时钟来处理第一子阶段的逻辑，而不管将第二时钟提供给交换机流水线阶段内的第二子阶段的处理逻辑。与当前交换流水线级相关联的时钟逻辑可以响应于先前流水线级对分组数据的处理来接收诸如来自先前流水线级的事件指示的事件指示。作为响应，与当前交换流水线级相关联的时钟逻辑可以确定在当前交换流水线级中向所选流水线子级发出时钟的时钟时间。时钟逻辑还可以在时钟时间向所选流水线子级发出时钟。

6. 发明申请

US20130086074A1 EXTENDED WIDTH ENTRIES FOR HASH TABLES 失效
标题翻译：扩展的宽度入口用于表格
公开(公告)号：US20130086074A1
公开(公告)日：2013-04-04
申请号：US13249793
申请日：2011-09-30
申请人： Brandon C. Smith , John J. Dull , Vamsi Tatapudi
发明人： Brandon C. Smith , John J. Dull , Vamsi Tatapudi
IPC分类号： G06F17/30
CPC分类号： G06F17/30949 , H04L45/7453
摘要： A hash table supports extended entries. The extended entries permit a base entry to extend its associated data into one or more neighboring entries. Extended entries thereby provide a mechanism through which a hash table entry may store additional data compared to a base entry. Extended entries may coexist with base entries in the hash table. The hash table thereby provides the flexibility to adapt dynamically to meet system requirements and to balance the needs of additional data storage by blending the number of extended entries (that each store more data than a base entry) and the number of base entries (each storing less data than an extended entry).
摘要翻译：哈希表支持扩展条目。扩展条目允许基本条目将其相关联的数据扩展到一个或多个相邻条目。因此，扩展条目提供了一种机制，散列表条目可以与基本条目相比较地存储附加数据。扩展条目可能与哈希表中的基本条目共存。因此，散列表提供了灵活性，以动态地适应以满足系统需求，并且通过混合扩展条目的数量（每个存储比基本条目更多的数据）和基本条目的数量（每个存储少于扩展条目的数据）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式