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1. 发明申请

US20070273643A1 Dongle joystick 审中-公开
标题翻译：东尔操纵杆
公开(公告)号：US20070273643A1
公开(公告)日：2007-11-29
申请号：US11716648
申请日：2007-03-12
申请人： Eran Erez , Ran Carmeli , Moshe Raines , Yitzhak Pomerantz
发明人： Eran Erez , Ran Carmeli , Moshe Raines , Yitzhak Pomerantz
IPC分类号： G09G5/00
CPC分类号： H04N5/775 , G05G2009/04729 , G06F3/0338
摘要： A portable data storage device (dongle) is configured to serve as a joystick. A method and system are supplied for using the dongle joystick to modify the presentation of an a electric media content item over a host and for using the dongle joystick as a user input interface to select a content item to be presented over a host or to select a datum to be stored. One portion of the dongle joystick is connected to the host and held stationary while a user imposes a force on a second part of the joystick to select and play content. The dongle joystick may include a processor to process output into a format compatible with a legacy playing device host.
摘要翻译：便携式数据存储设备（加密狗）被配置为用作操纵杆。提供一种方法和系统，用于使用加密狗操纵杆通过主机修改电子媒体内容项目的呈现，并且使用加密狗操纵杆作为用户输入接口来选择要通过主机呈现的内容项目或选择要存储的基准。加密狗操纵杆的一部分连接到主机并保持静止，而用户在操纵杆的第二部分施加力以选择和播放内容。加密狗操纵杆可以包括处理器以将输出处理成与传统播放设备主机兼容的格式。

2. 发明授权

US08041879B2 Flash memory backup system and method 有权
标题翻译：闪存备份系统和方法
公开(公告)号：US08041879B2
公开(公告)日：2011-10-18
申请号：US11318863
申请日：2005-12-28
申请人： Eran Erez
发明人： Eran Erez
IPC分类号： G06F11/16 , G06F11/00
CPC分类号： G11C11/005 , G11C16/10 , G11C16/16 , G11C2216/14
摘要： A flash memory system includes a flash controller for controlling operation of at least two flash memory devices. A page buffer is allocated within each flash memory device, such that one page buffer functions as a designated target buffer and another page buffer functions as a mirror buffer. The flash controller transmits the page data to two flash memory devices simultaneously, such that no backup of the page data is required to be kept in the flash controller. Hence, there is no delay in writing the next page data from a host computer to the flash controller.
摘要翻译：闪存系统包括用于控制至少两个闪存设备的操作的闪存控制器。在每个闪速存储器件内分配页面缓冲器，使得一个页面缓冲器用作指定的目标缓冲器，另一个页面缓冲器用作镜像缓冲器。闪存控制器将页面数据同时发送到两个闪存设备，使得不需要将页面数据的备份保存在闪存控制器中。因此，将下一页数据从主机写入闪存控制器是没有延迟的。

3. 发明申请

US20080059692A1 Device for prioritized erasure of flash memory 有权
标题翻译：用于闪存优先擦除的设备
公开(公告)号：US20080059692A1
公开(公告)日：2008-03-06
申请号：US11797378
申请日：2007-05-03
申请人： Eran Erez
发明人： Eran Erez
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： A storage device having prioritized-erasure capabilities including: a memory for storing data, the memory having at least one flash unit, wherein each flash unit has a plurality of blocks; and a controller configured: to write the data into the plurality of blocks; to assign an erasure-priority to each block, wherein the erasure-priority correlates with an erasure-priority of the data; and to erase the data in each block according to the erasure-priority of each block upon receiving an emergency-erase command. Preferably, the controller is configured to perform the writing of the data into the plurality of blocks in an arbitrary order in a first flash unit, and the writing into subsequent flash units is performed in correlation with the order in the first flash unit. Preferably, the erasing includes aborting erasure, before completing the erasure, for at least some of the plurality of blocks.
摘要翻译：一种具有优先删除功能的存储设备，包括：用于存储数据的存储器，所述存储器具有至少一个闪存单元，其中每个闪存单元具有多个块; 以及控制器，被配置为：将所述数据写入所述多个块中; 为每个块分配擦除优先级，其中擦除优先级与数据的擦除优先级相关; 并且在接收到紧急擦除命令时根据每个块的擦除优先级擦除每个块中的数据。优选地，控制器被配置为在第一闪存单元中以任意顺序执行数据到多个块中的写入，并且与第一闪存单元中的顺序相关地执行对后续闪存单元的写入。优选地，擦除包括在完成擦除之前针对多个块中的至少一些块中止擦除。

4. 发明申请

US20060152173A1 Method and apparatus for intentionally damaging a solid-state disk 审中-公开
标题翻译：有意损坏固态磁盘的方法和装置
公开(公告)号：US20060152173A1
公开(公告)日：2006-07-13
申请号：US11113153
申请日：2005-04-25
申请人： Eran Erez
发明人： Eran Erez
IPC分类号： H05B41/36
CPC分类号： G06F21/79 , G06F3/0601 , G06F2003/0692 , G11C16/22
摘要： A device and method for disabling one or more memory components of a solid state memory device such as a NAND flash memory device is provided. In some embodiments, the presently disclosed memory device includes a damaging mechanism operative to physically damage a memory component. In a particular embodiment, the memory component to be damaged includes at least one pin, and the damaging mechanism is operative to apply a voltage to at least one pin sufficient to damage one or more memory components. In some embodiments, the damaging mechanism is activated in accordance with one or more specific software commands and/or hardware signals. Optionally, the presently disclosed device includes a prioritizing mechanism for prioritizing an order in which specific memory components are damaged by the damaging mechanism.
摘要翻译：提供了一种用于禁止诸如NAND快闪存储器件的固态存储器件的一个或多个存储器组件的装置和方法。在一些实施例中，本公开的存储器件包括可操作以物理损坏存储器部件的损坏机构。在特定实施例中，待损坏的存储器组件包括至少一个引脚，并且损坏机构可操作以将电压施加到足以损坏一个或多个存储器组件的至少一个引脚。在一些实施例中，损坏机制根据一个或多个特定的软件命令和/或硬件信号被激活。可选地，本公开的设备包括优先级排序机制，用于对特定存储器组件被损坏机制损坏的顺序进行优先级排序。

5. 发明申请

US20060006818A1 Process for operating a discharge lamp 失效
标题翻译：操作放电灯的过程
公开(公告)号：US20060006818A1
公开(公告)日：2006-01-12
申请号：US11169727
申请日：2005-06-30
申请人： Omri Fishbein , Eran Erez
发明人： Omri Fishbein , Eran Erez
IPC分类号： G05F1/00
CPC分类号： H05B41/2885 , Y02B20/202
摘要： There is provided a process for operating a High Intensity Discharge (HID) lamp, having stable and transient operating phases, by a digitally controlled circuit that includes a DC supply and an inverter. During the stable operating phase of the lamp, the inverter's input DC voltage is maintained at a value depending on the lamp voltage.
摘要翻译：提供了一种通过包括直流电源和逆变器的数字控制电路来操作具有稳定和瞬态工作阶段的高强度放电（HID）灯的过程。在灯的稳定运行阶段，逆变器的输入直流电压保持在一个取决于灯电压的值。

6. 发明授权

US09134918B2 Physical compression of data with flat or systematic pattern 有权
标题翻译：具有平坦或系统模式的数据的物理压缩
公开(公告)号：US09134918B2
公开(公告)日：2015-09-15
申请号：US12651133
申请日：2009-12-31
申请人： Damian P. Yurzola , Sergey A. Gorobets , Neil D. Hutchison , Eran Erez
发明人： Damian P. Yurzola , Sergey A. Gorobets , Neil D. Hutchison , Eran Erez
IPC分类号： G06F3/06 , G06F12/02
CPC分类号： G06F3/0652 , G06F3/0608 , G06F3/0616 , G06F3/0641 , G06F3/0679 , G06F12/0246 , G06F2212/401 , G06F2212/7205 , G06F2212/7209
摘要： Systems and methods are disclosed to improve the performance of a memory system by freeing up physical memory areas that correspond to logical block address ranges that have repeated data patterns. A controller detects data patterns in incoming data. When a data pattern is detected, the data is not written to non-volatile storage area. Rather, the logical block address range of the data is marked in a data structure as having pattern data. The pattern may also be recorded in the data structure as a pattern descriptor. Because the data having the data pattern is not written to the non-volatile storage area, the freed up corresponding physical memory area may be utilized by the memory system for other purposes, thereby improving the overall performance and endurance of the memory system.
摘要翻译：公开了系统和方法，以通过释放对应于具有重复数据模式的逻辑块地址范围的物理存储器区域来改善存储器系统的性能。控制器检测输入数据中的数据模式。当检测到数据模式时，不将数据写入非易失性存储区域。相反，数据的逻辑块地址范围在数据结构中被标记为具有模式数据。模式也可以作为模式描述符记录在数据结构中。由于具有数据模式的数据未被写入非易失性存储区域，所以释放的对应的物理存储器区域可被存储系统用于其他目的，从而提高存储系统的整体性能和耐久性。

7. 发明授权

US08234539B2 Correction of errors in a memory array 有权
标题翻译：更正存储器阵列中的错误
公开(公告)号：US08234539B2
公开(公告)日：2012-07-31
申请号：US11951455
申请日：2007-12-06
申请人： Eran Erez
发明人： Eran Erez
IPC分类号： H03M13/00
CPC分类号： G06F11/1068
摘要： A computer system for correction of errors in a memory array includes an error correction algorithm and a memory. The error correction algorithm is capable of correcting errors up to a first bit error rate in a correctable group of memory cells having a standard size. The memory is operative to store a first set of ECC bits having information corresponding to a first group of memory cells having a first size larger than the standard size, and to store a second set of ECC bits having information corresponding to a second group of memory cells having a second size smaller than said first size and being a portion of said first group. The error correction algorithm is operative to correct errors in the second group based on the second set of ECC bits if a failure occurs in correction of the first group based on the first set of ECC bits.
摘要翻译：用于校正存储器阵列中的错误的计算机系统包括纠错算法和存储器。纠错算法能够在具有标准尺寸的可校正组的存储器单元中校正高达第一误码率的误差。存储器用于存储具有对应于具有大于标准尺寸的第一大小的第一组存储器单元的信息的第一组ECC位，并且存储具有对应于第二组存储器的信息的第二组ECC位具有小于所述第一尺寸的第二尺寸并且是所述第一组的一部分的单元。如果基于第一组ECC位的第一组的校正发生故障，则纠错算法可用于基于第二组ECC比特来校正第二组中的错误。

8. 发明申请

US20120017138A1 Adaptive Flash Interface 有权
标题翻译：自适应闪存接口
公开(公告)号：US20120017138A1
公开(公告)日：2012-01-19
申请号：US12835292
申请日：2010-07-13
申请人： Eran Erez , Steven Shisan Cheng
发明人： Eran Erez , Steven Shisan Cheng
IPC分类号： G11C29/52 , G06F11/00
CPC分类号： G06F11/1004 , G06F11/221 , G11C7/10 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C29/022 , G11C29/028 , G11C2029/0411
摘要： A structure, and corresponding operating techniques, are presented for the internal controller to memory circuit interface for memory systems such a flash memory card or other similarly structured devices. The interface between the controller circuit and memory circuit (or circuits) includes a feedback process where the amount of error that arises due to controller-memory transfers is monitored and the transfer characteristics (such as clock rate, drive strength, etc.) can be modified accordingly. For example, in addition to transferring a set of data, the transmitting side also generates and transmits a corresponding hash value for the set of data. When the set of data is received on the other side, a hash value is also generated there and compared to the received hash value to determine if these was transmission error. If there is no error, the transfer rate could, for example, be increased, while if there were error, it could be decreased.
摘要翻译：为内部控制器提供了一种结构和相应的操作技术，用于诸如闪存卡或其他类似结构的设备之类的存储器系统的存储器电路接口。控制器电路和存储器电路（或电路）之间的接口包括反馈过程，其中监控由于控制器 - 存储器传输引起的错误量，并且传输特性（诸如时钟速率，驱动强度等）可以是相应修改。例如，除了传送一组数据之外，发送侧还生成并发送该组数据的相应散列值。当在另一侧接收到该组数据时，也在其上生成哈希值并与接收的散列值进行比较以确定这些是否是传输错误。如果没有错误，则可以例如增加传输速率，而如果存在错误，则可以减少传输速率。

9. 发明授权

US07779217B2 Systems for optimizing page selection in flash-memory devices 有权
标题翻译：用于优化闪存设备中页面选择的系统
公开(公告)号：US07779217B2
公开(公告)日：2010-08-17
申请号：US11772218
申请日：2007-06-30
申请人： Eran Erez
发明人： Eran Erez
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7202 , G11C8/12 , G11C11/5621
摘要： A storage device is provided. The storage device includes a memory that includes interleaved fast and slow pages and a controller. In response to a command from a host of the storage device the controller stores fast-reading data in the memory. If the fast and slow pages alternate, the controller stores the fast-reading data in the first pages alternately with filler data in the low pages, and if contiguous pluralities of the fast and slow pages alternate, the controller stores the fast reading data in the contiguous pluralities of the fast pages alternately with the filler data in the contiguous pluralities of the slow pages.
摘要翻译：提供存储设备。存储装置包括包括交错的快速和慢速页面的存储器和控制器。响应于存储设备的主机的命令，控制器将快速读取数据存储在存储器中。如果快速和慢速页面交替，则控制器将第一页中的快速读取数据与低页面中的填充数据交替存储，并且如果连续的多个快速和慢速页面交替，则控制器将快速读取数据存储在连续多个快速页面与连续多个慢页面中的填充数据交替。

10. 发明授权

US07525870B2 Methods for optimizing page selection in flash-memory devices 有权
标题翻译：闪存设备中优化页面选择的方法
公开(公告)号：US07525870B2
公开(公告)日：2009-04-28
申请号：US11772223
申请日：2007-06-30
申请人： Eran Erez
发明人： Eran Erez
IPC分类号： G11C7/00
CPC分类号： G06F12/0246 , G06F2212/7202 , G11C8/12 , G11C11/5621
摘要： The present invention discloses methods for storing data in a flash-memory storage device, the method including the steps of: receiving, by the device, primary data to be stored in the device and to be read from the device at a primary reading speed; storing at least part of the primary data only in fast pages in the device, wherein the fast pages are located in multi-level cells of the device; designating, by the device, secondary data to be read from the device at a secondary reading speed, wherein the secondary reading speed is slower than the primary reading speed; and storing at least part of the secondary data only in slow pages in the device, wherein the slow pages are located in the multi-level cells. Preferably, the method further includes the step of: moving the secondary data from a previously-stored area in the device to the slow pages.
摘要翻译：本发明公开了一种在闪速存储器存储装置中存储数据的方法，该方法包括以下步骤：由设备接收存储在设备中并以初级读取速度从设备读取的主数据; 将至少部分主要数据仅存储在设备中的快速页面中，其中快速页面位于设备的多级单元中; 由所述装置指定要以二次读取速度从所述装置读取的辅助数据，其中所述次要读取速度慢于所述主要读取速度; 并且仅将第二数据的至少一部分存储在设备中的慢页中，其中慢页位于多级单元中。优选地，该方法还包括以下步骤：将辅助数据从设备中的先前存储的区域移动到慢速页面。

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