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1. 发明申请

US20080052646A1 LITHOGRAPHY AWARE LEAKAGE ANALYSIS 有权
标题翻译： LITHOGRAPHY AWARE泄漏分析
公开(公告)号：US20080052646A1
公开(公告)日：2008-02-28
申请号：US11781043
申请日：2007-07-20
申请人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
发明人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F17/5068 , G06F2217/12
摘要： A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
摘要翻译：执行泄漏分析的方法包括接收指定集成电路的信息。然后确定与集成电路相关联的形状的邻域。基于形状附近生成与集成电路相关联的泄漏信息。可以通过从内部形状确定第一单元的边界的第一组间距来确定形状的邻域。可以从第一单元的边界到第二单元的形状来确定第二组间隔。可以使用第一和第二组间隔来表征光刻工艺。

2. 发明授权

US08572523B2 Lithography aware leakage analysis 有权
标题翻译：光刻感知泄漏分析
公开(公告)号：US08572523B2
公开(公告)日：2013-10-29
申请号：US11781043
申请日：2007-07-20
申请人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
发明人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F17/5068 , G06F2217/12
摘要： A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
摘要翻译：执行泄漏分析的方法包括接收指定集成电路的信息。然后确定与集成电路相关联的形状的邻域。基于形状附近生成与集成电路相关联的泄漏信息。可以通过从内部形状确定第一单元的边界的第一组间距来确定形状的邻域。可以从第一单元的边界到第二单元的形状来确定第二组间隔。可以使用第一和第二组间隔来表征光刻工艺。

3. 发明授权

US08473876B2 Lithography aware timing analysis 有权
标题翻译：光刻感知时序分析
公开(公告)号：US08473876B2
公开(公告)日：2013-06-25
申请号：US11781054
申请日：2007-07-20
申请人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
发明人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
摘要翻译：一种执行定时分析的方法包括接收指定集成电路的信息。然后确定与集成电路相关联的形状的邻域。基于形状附近生成与集成电路相关联的延迟信息。可以通过从内部形状确定第一单元的边界的第一组间距来确定形状的邻域。可以从第一单元的边界到第二单元的形状来确定第二组间隔。可以使用第一和第二组间隔来表征光刻工艺。

4. 发明申请

US20080052653A1 LITHOGRAPHY AWARE TIMING ANALYSIS 有权
公开(公告)号：US20080052653A1
公开(公告)日：2008-02-28
申请号：US11781054
申请日：2007-07-20
申请人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
发明人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
摘要翻译：一种执行定时分析的方法包括接收指定集成电路的信息。然后确定与集成电路相关联的形状的邻域。基于形状附近生成与集成电路相关联的延迟信息。可以通过从内部形状确定第一单元的边界的第一组间距来确定形状的邻域。可以从第一单元的边界到第二单元的形状来确定第二组间隔。可以使用第一和第二组间隔来表征光刻工艺。

5. 发明授权

US07434188B1 Lithographically optimized placement tool 有权
标题翻译：光刻优化的放置工具
公开(公告)号：US07434188B1
公开(公告)日：2008-10-07
申请号：US11372557
申请日：2006-03-09
申请人： Anirudh Devgan , Roderick Metcalfe , Vivek Raghavan , Alfred Wong
发明人： Anirudh Devgan , Roderick Metcalfe , Vivek Raghavan , Alfred Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system and a method are disclosed for integrating the results of lithographic simulation into the physical synthesis process. The effects of lithographic variation are considered when selecting a cell from among a group of cells having equivalent function. Circuit design elements are placed and routed with consideration of the effects of lithographic variation on robustness, timing performance, and leakage current. Cells may be simulated under a variety of conditions and environments and the simulation results stored in a library for efficient lithographically optimized placements.
摘要翻译：公开了一种用于将光刻仿真的结果集成到物理合成过程中的系统和方法。从具有等效功能的一组细胞中选择细胞时，考虑光刻变化的影响。考虑到光刻变化对鲁棒性，时序性能和漏电流的影响，电路设计元件被放置和布线。可以在各种条件和环境下模拟细胞，并将模拟结果存储在库中以进行有效的光刻优化的放置。

6. 发明授权

US06286126B1 Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits using best and worst case delay models for nets therein 有权
标题翻译：用于对其中的网络使用最佳和最差情况延迟模型执行微电子电路的布局后验证的方法，装置和计算机程序产品
公开(公告)号：US06286126B1
公开(公告)日：2001-09-04
申请号：US09292783
申请日：1999-04-13
申请人： Vivek Raghavan , Brian A. Zimmerman
发明人： Vivek Raghavan , Brian A. Zimmerman
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： Methods, apparatus and computer program products are provided that perform the operations of extracting first estimates of the resistance and capacitance of each of a first plurality of nets in an integrated circuit and then determining, for each of the first plurality of nets, a respective maximum delay model that attributes all of the first estimate of the resistance of the respective net to a front-end of the net and all of the first estimate of the capacitance of the respective net to a back-end of the net. Respective minimum delay models are also obtained for each of the first plurality of nets. Each of these minimum delay models attributes all of the first estimate of the resistance of the respective net to the back-end of the net and all of the first estimate of the capacitance of the respective net to a front-end of the net. These minimum and maximum delay models are then used in the determination of minimum and maximum delay estimates for each of the first plurality of nets. The delay estimates are then used to determine a net timing error bound associated with each net. These net timing error bounds are then filtered against a user-specified net timing error tolerance to determine which nets have an excessive timing error bound. Those nets having excessive timing error bounds are then modeled using more accurate models.
摘要翻译：提供了方法，装置和计算机程序产品，其执行提取集成电路中的第一多个网络中的每一个的电阻和电容的第一估计的操作，然后针对第一多个网络中的每个网络确定相应的最大值延迟模型将所有对网的电阻的第一估计值和网的前端的所有第一估计值以及相应网络的电容的所有第一估计值归因于网的后端。对于第一多个网络中的每个网络也获得了相应的最小延迟模型。这些最小延迟模型中的每个都将相应网络的电阻的所有第一估计值与网络的后端相关联，并且将相应网络的电容的所有第一估计值与网络的前端进行归因。然后，这些最小和最大延迟模型用于确定第一多个网络中的每个网络的最小和最大延迟估计。然后使用延迟估计来确定与每个网络相关联的净定时误差界限。然后根据用户指定的净定时误差容限对这些净定时误差范围进行滤波，以确定哪些网络具有过大的定时误差限制。然后使用更准确的模型对具有过多时间误差界限的网络进行建模。

7. 发明授权

US5313398A Method and apparatus for simulating a microelectronic circuit 失效
标题翻译：用于模拟微电子电路的方法和装置
公开(公告)号：US5313398A
公开(公告)日：1994-05-17
申请号：US919160
申请日：1992-07-23
申请人： Ronald A. Rohrer , Vivek Raghavan , J. Eric Bracken
发明人： Ronald A. Rohrer , Vivek Raghavan , J. Eric Bracken
IPC分类号： G06F17/50 , G06F15/20
CPC分类号： G06F17/5036
摘要： A method and apparatus for simulating a microelectronic circuit includes the steps of storing of a microelectronic circuit or system representation in a computer system and then dividing the circuit or system into portions containing nonlinear elements and linear partitions. The linear partitions are then independently solved for by modelling each linear partition using Asymptotic Waveform Evaluation (AWE) to form multiport admittance macromodels. These macromodels provide admittance and current stencils, which may be functions of time, to a global MNA matrix used by SPICE at each time point to simulate the operation of the entire microelectronic circuit. A linearized transient representation for the nonlinear elements is provided as SPICE admittance and current stencils using conventional techniques. By using AWE techniques to solve the linear partitions separately, significant savings in computation time and improved computational storage efficiency can be achieved.
摘要翻译：用于模拟微电子电路的方法和装置包括以下步骤：将微电子电路或系统表示存储在计算机系统中，然后将电路或系统分成包含非线性元件和线性分区的部分。然后通过使用渐近波形评估（AWE）对每个线性分区建模以形成多端口导纳宏模型，独立地求解线性分区。这些宏模型可以将SPICE在每个时间点使用的全局MNA矩阵提供可能是时间的功能的导纳和当前模板，以模拟整个微电子电路的操作。非线性元件的线性化瞬态表示法使用常规技术作为SPICE导纳和电流模板提供。通过使用AWE技术分别解决线性分区，可以显着节省计算时间并提高计算存储效率。

8. 发明授权

US5896300A Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits by filtering timing error bounds for layout critical nets 失效
标题翻译：用于通过过滤布局关键网络的定时误差范围来执行微电子电路的布局后验证的方法，装置和计算机程序产品
公开(公告)号：US5896300A
公开(公告)日：1999-04-20
申请号：US706182
申请日：1996-08-30
申请人： Vivek Raghavan , Brian Allan Zimmerman
发明人： Vivek Raghavan , Brian Allan Zimmerman
IPC分类号： H01L21/82 , G06F17/50 , G06F17/00
CPC分类号： G06F17/5022
摘要： A method, apparatus and computer program product performs a bounded parasitic extraction of typically all nets in an integrated circuit as part of a series of post-layout verification operations. According to one embodiment, a resistance-only extraction and/or a capacitance-only extraction is initially performed using computationally inexpensive electrical models of the nets. The resistance and capacitance extractions may be combined with models of the active devices to generate realistic worst case and best case delay models for each of the extracted nets. The delay models may be based on the resistance-only extraction and an upper bound on the parasitic capacitance of the net determined from the capacitance-only extraction, however, other models based solely on a resistance-only extraction may also be used, although they are typically less preferred. A user-specified timing error tolerance is then used to automatically determine the appropriate level of additional extraction detail to be applied to the specific nets in the integrated circuit. This gives the user direct error control over the extraction process so that the extracted netlist meets the user-specified timing error tolerance in an efficient manner.
摘要翻译：作为一系列后布局验证操作的一部分，方法，装置和计算机程序产品执行集成电路中通常所有网络的有界寄生提取。根据一个实施例，首先使用网络的计算上便宜的电气模型来执行仅电阻提取和/或仅电容提取。电阻和电容提取可以与有源器件的模型组合以产生用于每个提取的网络的逼真的最坏情况和最佳情况延迟模型。延迟模型可以基于电阻提取和由仅电容提取确定的网络的寄生电容的上限，然而，也可以使用仅基于电阻提取的其它模型，尽管它们通常不太优选。然后，用户指定的定时误差容限用于自动确定要应用于集成电路中特定网络的附加提取细节的适当级别。这提供了用户对提取过程的直接错误控制，使得提取的网表以有效的方式满足用户指定的定时误差容限。

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