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1. 发明授权

US08508266B2 Digital phase locked loop circuits with multiple digital feedback loops 有权
标题翻译：具有多个数字反馈回路的数字锁相环电路
公开(公告)号：US08508266B2
公开(公告)日：2013-08-13
申请号：US13173694
申请日：2011-06-30
申请人： Emmanouil Frantzeskakis , Georgios Sfikas , Stephen Wu , Radha Srinivasan , Henrik Tholstrup Jensen , Brima Ibrahim
发明人： Emmanouil Frantzeskakis , Georgios Sfikas , Stephen Wu , Radha Srinivasan , Henrik Tholstrup Jensen , Brima Ibrahim
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , H03L7/18
摘要： Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.
摘要翻译：具有数字锁相环（DPLL）电路的器件的设计包括多个数字反馈回路，以通过数字控制振荡器（DCO）产生高频时钟信号。在这种DPLL电路中提供时间数字转换器（TDC）模块，以从第一数字反馈回路接收输入参考时钟信号和第一反馈时钟信号，并产生指示第一相位误差的数字TDC输出通过输入参考时钟信号和第一反馈时钟信号之间的时间差。提供第二数字反馈环路以产生指示由期望时钟信号和由DCO产生的生成的时钟信号之间的频率差引起的第二相位误差的第二数字反馈信号。第一和第二数字反馈回路耦合到DCO以产生高频时钟信号。

2. 发明申请

US20130002317A1 DIGITAL PHASE LOCKED LOOP CIRCUITS WITH MULTIPLE DIGITAL FEEDBACK LOOPS 有权
标题翻译：数字相位锁定电路与多个数字反馈灯
公开(公告)号：US20130002317A1
公开(公告)日：2013-01-03
申请号：US13173694
申请日：2011-06-30
申请人： Emmanouil Frantzeskakis , Georgios Sfikas , Stephen Wu , Radha Srinivasan , Henrik Tholstrup Jensen , Brima Ibrahim
发明人： Emmanouil Frantzeskakis , Georgios Sfikas , Stephen Wu , Radha Srinivasan , Henrik Tholstrup Jensen , Brima Ibrahim
IPC分类号： H03L7/08
CPC分类号： H03L7/08 , H03L7/18
摘要： Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.
摘要翻译：具有数字锁相环（DPLL）电路的器件的设计包括多个数字反馈回路，以通过数字控制振荡器（DCO）产生高频时钟信号。在这种DPLL电路中提供时间数字转换器（TDC）模块，以从第一数字反馈回路接收输入参考时钟信号和第一反馈时钟信号，并产生指示第一相位误差的数字TDC输出通过输入参考时钟信号和第一反馈时钟信号之间的时间差。提供第二数字反馈环路以产生指示由期望时钟信号和由DCO产生的生成的时钟信号之间的频率差引起的第二相位误差的第二数字反馈信号。第一和第二数字反馈回路耦合到DCO以产生高频时钟信号。

3. 发明申请

US20100009673A1 METHOD AND SYSTEM FOR FREQUENCY FEEDBACK ADJUSTMENT IN DIGITAL RECEIVERS 有权
标题翻译：数字接收机频率反馈调整方法与系统
公开(公告)号：US20100009673A1
公开(公告)日：2010-01-14
申请号：US12563765
申请日：2009-09-21
申请人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen
发明人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen
IPC分类号： H04W24/00
CPC分类号： H03J7/02 , H03J2200/02 , H04L25/063 , H04L27/142 , H04L2027/0057 , H04L2027/0065
摘要： In RF transceivers, a method and a system for a frequency feedback adjustment in digital receivers are provided. A DC offset may result from the difference in frequencies between an RF transmitter and an RF receiver. An adjustment of the receiver's frequency may be implemented after synchronization occurs and may be performed by, for example, utilizing a header portion of a packet communicated via a wireless interface. The adjustment may be performed when the frequency difference exceeds a threshold value. In another aspect, adjusting the frequency of the RF receiver may be performed by modifying and/or changing a phase locked loop (PLL) trimmer register. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.
摘要翻译：在RF收发器中，提供了一种用于数字接收机中的频率反馈调整的方法和系统。 DC偏移可能由RF发射机和RF接收机之间的频率差引起。接收机频率的调整可以在同步发生之后实现，并且可以通过例如利用经由无线接口传送的分组的报头部分来执行。当频率差超过阈值时，可以进行调整。在另一方面，可以通过修改和/或改变锁相环（PLL）微调寄存器来调整RF接收机的频率。这种方法可以允许RF接收机在某些情况下操作，而不需要均衡器。在这方面，RF接收机消耗的功率可以被最小化，和/或可以降低RF接收机的总体成本。

4. 发明申请

US20080214112A1 Method and System for Using PSK Sync Word for Fine Tuning Frequency Adjustment 有权
标题翻译：使用PSK Sync Word进行微调频率调整的方法和系统
公开(公告)号：US20080214112A1
公开(公告)日：2008-09-04
申请号：US12052214
申请日：2008-03-20
申请人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen , Siukai Mak
发明人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen , Siukai Mak
IPC分类号： H04B7/00 , H04B1/16
CPC分类号： H04L25/063 , H04L27/22 , H04L2027/003 , H04L2027/0057 , H04L2027/0095
摘要： In RF transceivers, a method and system for using phase shift key (PSK) sync word for fine tuning frequency adjustment are provided. One aspect of the invention provides for adjusting a local oscillator frequency in a radio frequency (RF) receiver when a residual DC offset remains after a coarse frequency offset adjustment if performed. The fine adjustment may be necessary because of the synchronization required with a PSK-based modulated portion of a Bluetooth packet. A residual phase shift detected in a sync sequence portion of the Bluetooth packet may be utilized to determine a residual or fine frequency adjustment. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.
摘要翻译：在RF收发器中，提供了一种使用相移键（PSK）同步字进行微调频率调整的方法和系统。本发明的一个方面提供了当在执行粗频率偏移调整之后剩余DC偏移保留时，调整射频（RF）接收机中的本地振荡器频率。由于蓝牙分组的基于PSK的调制部分所需的同步，因此可能需要进行微调。在蓝牙分组的同步序列部分中检测到的残余相移可用于确定残差或精细频率调整。这种方法可以允许RF接收机在某些情况下操作，而不需要均衡器。在这方面，RF接收机消耗的功率可以被最小化，和/或可以降低RF接收机的总体成本。

5. 发明授权

US08081714B2 Method and system for reuse of CORDIC in an RF transceiver by reconfiguration in real time 有权
标题翻译： CORDIC在RF收发器中实时重配置的方法和系统
公开(公告)号：US08081714B2
公开(公告)日：2011-12-20
申请号：US10989536
申请日：2004-11-16
申请人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen , Paul Lettieri , Siukai Mak
发明人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen , Paul Lettieri , Siukai Mak
IPC分类号： H04L27/00
CPC分类号： H03D3/006
摘要： Methods and systems for processing an RF signal are disclosed herein. Aspects of the method may comprise utilizing a single input CORDIC and a single output CORDIC for synchronizing and demodulating a received signal, wherein the received signal may comprise one or more bit rates. The received signal may comprise a one megabit per second (Mbps) signal. The single input CORDIC may be configured to operate in a rotating mode and the single output CORDIC may be configured to operate in a rotating mode and/or an arctangent (ARCTAN) mode. A rotated output of the single input CORDIC may be correlated with a phase shift keying (PSK) synchronization (sync) word and a portion of the correlated rotated output of the single input CORDIC may be buffered.
摘要翻译：本文公开了用于处理RF信号的方法和系统。该方法的方面可以包括利用单个输入CORDIC和单个输出CORDIC来同步和解调所接收的信号，其中所接收的信号可以包括一个或多个比特率。所接收的信号可以包括一兆兆比特每秒（Mbps）信号。单输入CORDIC可以被配置为以旋转模式操作，并且单输出CORDIC可以被配置为在旋转模式和/或反正切（ARCTAN）模式下操作。单输入CORDIC的旋转输出可以与相移键控（PSK）同步（sync）字相关，并且单个输入CORDIC的相关旋转输出的一部分可以被缓冲。

6. 发明授权

US08050647B2 Method and system for frequency feedback adjustment in digital receivers 有权
标题翻译：数字接收机频率反馈调整方法及系统
公开(公告)号：US08050647B2
公开(公告)日：2011-11-01
申请号：US12563765
申请日：2009-09-21
申请人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen
发明人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen
IPC分类号： H04B1/20
CPC分类号： H03J7/02 , H03J2200/02 , H04L25/063 , H04L27/142 , H04L2027/0057 , H04L2027/0065
摘要： In RF transceivers, a method and a system for a frequency feedback adjustment in digital receivers are provided. A DC offset may result from the difference in frequencies between an RF transmitter and an RF receiver. An adjustment of the receiver's frequency may be implemented after synchronization occurs and may be performed by, for example, utilizing a header portion of a packet communicated via a wireless interface. The adjustment may be performed when the frequency difference exceeds a threshold value. In another aspect, adjusting the frequency of the RF receiver may be performed by modifying and/or changing a phase locked loop (PLL) trimmer register. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.
摘要翻译：在RF收发器中，提供了用于数字接收机中的频率反馈调整的方法和系统。 DC偏移可能由RF发射机和RF接收机之间的频率差引起。接收机频率的调整可以在同步发生之后实现，并且可以通过例如利用经由无线接口传送的分组的报头部分来执行。当频率差超过阈值时，可以进行调整。在另一方面，可以通过修改和/或改变锁相环（PLL）微调寄存器来调整RF接收机的频率。这种方法可以允许RF接收机在某些情况下操作，而不需要均衡器。在这方面，RF接收机消耗的功率可以被最小化，和/或可以降低RF接收机的总体成本。

7. 发明授权

US07349680B2 Method and system for using PSK sync word for fine tuning frequency adjustment 有权
标题翻译：使用PSK同步字进行微调频率调整的方法和系统
公开(公告)号：US07349680B2
公开(公告)日：2008-03-25
申请号：US11101961
申请日：2005-04-08
申请人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen , Siukai Mak
发明人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen , Siukai Mak
IPC分类号： H04B1/26
CPC分类号： H04L25/063 , H04L27/22 , H04L2027/003 , H04L2027/0057 , H04L2027/0095
摘要： In RF transceivers, a method and system for using phase shift key (PSK) sync word for fine tuning frequency adjustment are provided. One aspect of the invention provides for adjusting a local oscillator frequency in a radio frequency (RF) receiver when a residual DC offset remains after a coarse frequency offset adjustment if performed. The fine adjustment may be necessary because of the synchronization required with a PSK-based modulated portion of a Bluetooth packet. A residual phase shift detected in a sync sequence portion of the Bluetooth packet may be utilized to determine a residual or fine frequency adjustment. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.
摘要翻译：在RF收发器中，提供了一种使用相移键（PSK）同步字进行微调频率调整的方法和系统。本发明的一个方面提供了当在执行粗频率偏移调整之后剩余DC偏移保留时，调整射频（RF）接收机中的本地振荡器频率。由于蓝牙分组的基于PSK的调制部分所需的同步，因此可能需要进行微调。在蓝牙分组的同步序列部分中检测到的残余相移可用于确定残差或精细频率调整。这种方法可以允许RF接收机在某些情况下操作，而不需要均衡器。在这方面，RF接收机消耗的功率可以被最小化，和/或可以降低RF接收机的总体成本。

8. 发明授权

US07684519B2 Method and system for adjusting DC offset slice point in an RF receiver 有权
标题翻译：用于调整RF接收机中DC偏移片段的方法和系统
公开(公告)号：US07684519B2
公开(公告)日：2010-03-23
申请号：US11102157
申请日：2005-04-08
申请人： Hea Joung Kim , Brima Ibrahim , Henrik Tholstrup Jensen
发明人： Hea Joung Kim , Brima Ibrahim , Henrik Tholstrup Jensen
IPC分类号： H04L25/06 , H04L25/10
CPC分类号： H04L27/142 , H04L25/062
摘要： A method for adjusting a DC offset slice point in an RF receiver is provided and may comprise estimating DC offset using a combination of fast tracking of an input signal and slow tracking of an input signal. If both are used, the fast tracking may be executed prior to executing the slow tracking. The fast tracking may acquire synchronizing signals transmitted before a payload. Additionally, noise tolerance may be increased in the fast tracking and the slow tracking by using tracking envelopes. The fast tracking may average acquisition envelopes and tracking envelopes using a fast tracking weighting factor to a sum of the acquisition envelopes and a slow tracking weighting factor to a sum of the tracking envelopes. Additionally, the slow tracking may average the tracking envelopes.
摘要翻译：提供了一种用于调整RF接收机中的DC偏移切片点的方法，并且可以包括使用输入信号的快速跟踪和输入信号的慢跟踪的组合来估计DC偏移。如果使用两者，则可以在执行慢速跟踪之前执行快速跟踪。快速跟踪可以获取在有效载荷之前传输的同步信号。此外，通过使用跟踪包络，快速跟踪和慢速跟踪可能会增加噪声容限。快速跟踪可以使用快速跟踪加权因子将采集包络和跟踪包络平均为采集包络和缓慢跟踪加权因子之和到跟踪包络的总和。此外，慢速跟踪可以平均跟踪包络。

9. 发明授权

US07599662B2 Method and system for frequency feedback adjustment in digital receivers 有权
标题翻译：数字接收机频率反馈调整方法及系统
公开(公告)号：US07599662B2
公开(公告)日：2009-10-06
申请号：US11102123
申请日：2005-04-08
申请人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen
发明人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen
IPC分类号： H04B17/00 , H04B7/00
CPC分类号： H03J7/02 , H03J2200/02 , H04L25/063 , H04L27/142 , H04L2027/0057 , H04L2027/0065
摘要： In RF transceivers, a method and a system for a frequency feedback adjustment in digital receivers are provided. A DC offset may result from the difference in frequencies between an RF transmitter and an RF receiver. An adjustment of the receiver's frequency may be implemented after synchronization occurs and may be performed by utilizing the Forward Error Correction (FEC) repetition rate in a header of a Bluetooth packet. The adjustment may be performed when the frequency difference exceeds a threshold value. In another aspect, adjusting the frequency of the RF receiver may be performed by modifying and/or changing a phase locked loop (PLL) trimmer register. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.
摘要翻译：在RF收发器中，提供了用于数字接收机中的频率反馈调整的方法和系统。 DC偏移可能由RF发射机和RF接收机之间的频率差引起。可以在同步发生之后实现接收机频率的调整，并且可以通过利用蓝牙分组的报头中的前向纠错（FEC）重复率来执行。当频率差超过阈值时，可以进行调整。在另一方面，可以通过修改和/或改变锁相环（PLL）微调寄存器来调整RF接收机的频率。这种方法可以允许RF接收机在某些情况下操作，而不需要均衡器。在这方面，RF接收机消耗的功率可以被最小化，和/或可以降低RF接收机的总体成本。

10. 发明授权

US08112034B2 Method and system for using PSK sync word for fine tuning frequency adjustment 有权
标题翻译：使用PSK同步字进行微调频率调整的方法和系统
公开(公告)号：US08112034B2
公开(公告)日：2012-02-07
申请号：US12052214
申请日：2008-03-20
申请人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen , Siukai Mak
发明人： Brima Ibrahim , Hea Joung Kim , Henrik Tholstrup Jensen , Siukai Mak
IPC分类号： H04B7/00
CPC分类号： H04L25/063 , H04L27/22 , H04L2027/003 , H04L2027/0057 , H04L2027/0095
摘要： In RF transceivers, a method and system for using phase shift key (PSK) sync word for fine tuning frequency adjustment are provided. One aspect of the invention provides for adjusting a local oscillator frequency in a radio frequency (RF) receiver when a residual DC offset remains after a coarse frequency offset adjustment if performed. The fine adjustment may be necessary because of the synchronization required with a PSK-based modulated portion of a Bluetooth packet. A residual phase shift detected in a sync sequence portion of the Bluetooth packet may be utilized to determine a residual or fine frequency adjustment. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.
摘要翻译：在RF收发器中，提供了一种使用相移键（PSK）同步字进行微调频率调整的方法和系统。本发明的一个方面提供了当在执行粗频率偏移调整之后剩余DC偏移保留时，调整射频（RF）接收机中的本地振荡器频率。由于蓝牙分组的基于PSK的调制部分所需的同步，因此可能需要进行微调。在蓝牙分组的同步序列部分中检测到的残余相移可用于确定残差或精细频率调整。这种方法可以允许RF接收机在某些情况下操作，而不需要均衡器。在这方面，RF接收机消耗的功率可以被最小化，和/或可以降低RF接收机的总体成本。

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