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1. 发明申请

US20140189296A1 SYSTEM, APPARATUS AND METHOD FOR LOOP REMAINDER MASK INSTRUCTION 审中-公开
标题翻译：系统，装置和方法用于环路保护掩码指令
公开(公告)号：US20140189296A1
公开(公告)日：2014-07-03
申请号：US13993323
申请日：2011-12-14
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Andrey Naraikin , Suleyman Sair , Asaf Hargil , Miland B. Girkar , Bret T. Toll , Mark J. Charney
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Andrey Naraikin , Suleyman Sair , Asaf Hargil , Miland B. Girkar , Bret T. Toll , Mark J. Charney
IPC分类号： G06F9/38
CPC分类号： G06F9/3887 , G06F8/4441 , G06F9/30018 , G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/3013 , G06F9/325 , G06F9/3818 , G06F9/3824
摘要： A loop remainder mask instruction indicates a current iteration count of a loop as a first operand, an iteration limit of a loop as a second operand, and a destination. The loop contains iterations and each iteration includes a data element of the array. A processor receives the loop remainder mask instruction, decodes the instruction for execution, and stores a result of the execution in the destination. The result indicates a number of data elements of the array past an end of a preceding portion of the array that are to be handled separately from the preceding portion, the end of the preceding portion being where the current iteration count is recorded.
摘要翻译：循环余数掩码指令指示作为第一操作数的循环的当前迭代计数，作为第二操作数的循环的迭代限制以及目的地。循环包含迭代，每次迭代都包含数组的数据元素。处理器接收循环余数掩码指令，解码执行指令，并将执行结果存储在目的地。结果表示阵列的数据元素数目超过阵列的前一部分的结尾，与前一部分分开处理，前一部分的结尾是当前迭代计数的记录。

2. 发明申请

US20130232321A1 Unpacking Packed Data In Multiple Lanes 审中-公开
标题翻译：在多个车道中打包打包数据
公开(公告)号：US20130232321A1
公开(公告)日：2013-09-05
申请号：US13837908
申请日：2013-03-15
申请人： Asaf Hargil , Doron Orenstein
发明人： Asaf Hargil , Doron Orenstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30036
摘要： Receiving an instruction indicating first and second operands. Each of the operands having packed data elements that correspond in respective positions. A first subset of the data elements of the first operand and a first subset of the data elements of the second operand each corresponding to a first lane. A second subset of the data elements of the first operand and a second subset of the data elements of the second operand each corresponding to a second lane. Storing result, in response to instruction, including: (1) in first lane, only lowest order data elements from first subset of first operand interleaved with corresponding lowest order data elements from first subset of second operand; and (2) in second lane, only highest order data elements from second subset of first operand interleaved with corresponding highest order data elements from second subset of second operand.
摘要翻译：接收指示第一和第二操作数的指令。每个操作数具有在相应位置对应的数据元素的打包。第一操作数的数据元素的第一子集和第二操作数的数据元素的第一子集，每个对应于第一通道。所述第一操作数的数据元素的第二子集和所述第二操作数的数据元素的第二子集分别对应于第二通道。存储结果，响应于指令，包括：（1）在第一通道中，仅来自第一操作数的第一子集的最低顺序数据元素与来自第二操作数的第一子集的相应最低数据元素交织; 和（2）在第二通道中，仅来自第一操作数的第二子集的最高阶数据元素与来自第二操作数的第二子集的对应最高阶数据元素交织。

3. 发明授权

US08386547B2 Instruction and logic for performing range detection 有权
标题翻译：用于执行范围检测的指令和逻辑
公开(公告)号：US08386547B2
公开(公告)日：2013-02-26
申请号：US12290565
申请日：2008-10-31
申请人： Asaf Hargil , Evgeny Fiksman , Artiom Myaskouvskey , Doron Orenstien
发明人： Asaf Hargil , Evgeny Fiksman , Artiom Myaskouvskey , Doron Orenstien
IPC分类号： G06F7/00
CPC分类号： G06F17/17 , G06F9/30003
摘要： A technique to accelerate range detection in a spline calcuation. In one embodiment, an instruction and corresponding logic are provided to perform range detection within a computer or processor.
摘要翻译：一种在样条计算中加速范围检测的技术。在一个实施例中，提供指令和对应的逻辑以在计算机或处理器内执行范围检测。

4. 发明申请

US20100332794A1 UNPACKING PACKED DATA IN MULTIPLE LANES 有权
标题翻译：在多个土地上打包包装数据
公开(公告)号：US20100332794A1
公开(公告)日：2010-12-30
申请号：US12494667
申请日：2009-06-30
申请人： Asaf Hargil , Doron Orenstein
发明人： Asaf Hargil , Doron Orenstein
IPC分类号： G06F15/76
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30036
摘要： Receiving an instruction indicating first and second operands. Each of the operands having packed data elements that correspond in respective positions. A first subset of the data elements of the first operand and a first subset of the data elements of the second operand each corresponding to a first lane. A second subset of the data elements of the first operand and a second subset of the data elements of the second operand each corresponding to a second lane. Storing result, in response to instruction, including: (1) in first lane, only lowest order data elements from first subset of first operand interleaved with corresponding lowest order data elements from first subset of second operand; and (2) in second lane, only highest order data elements from second subset of first operand interleaved with corresponding highest order data elements from second subset of second operand.
摘要翻译：接收指示第一和第二操作数的指令。每个操作数具有在相应位置对应的数据元素的打包。第一操作数的数据元素的第一子集和第二操作数的数据元素的第一子集，每个对应于第一通道。所述第一操作数的数据元素的第二子集和所述第二操作数的数据元素的第二子集分别对应于第二通道。存储结果，响应于指令，包括：（1）在第一通道中，仅来自第一操作数的第一子集的最低顺序数据元素与来自第二操作数的第一子集的相应最低数据元素交织; 和（2）在第二通道中，仅来自第一操作数的第二子集的最高阶数据元素与来自第二操作数的第二子集的对应最高阶数据元素交织。

5. 发明授权

US09086872B2 Unpacking packed data in multiple lanes 有权
公开(公告)号：US09086872B2
公开(公告)日：2015-07-21
申请号：US12494667
申请日：2009-06-30
申请人： Asaf Hargil , Doron Orenstein
发明人： Asaf Hargil , Doron Orenstein
IPC分类号： G06F15/00 , G06F15/76 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30036
摘要： Receiving an instruction indicating first and second operands. Each of the operands having packed data elements that correspond in respective positions. A first subset of the data elements of the first operand and a first subset of the data elements of the second operand each corresponding to a first lane. A second subset of the data elements of the first operand and a second subset of the data elements of the second operand each corresponding to a second lane. Storing result, in response to instruction, including: (1) in first lane, only lowest order data elements from first subset of first operand interleaved with corresponding lowest order data elements from first subset of second operand; and (2) in second lane, only highest order data elements from second subset of first operand interleaved with corresponding highest order data elements from second subset of second operand.

6. 发明申请

US20100135417A1 PROCESSING OF VIDEO DATA IN RESOURCE CONTRAINED DEVICES 审中-公开
标题翻译：在资源受限制的设备中处理视频数据
公开(公告)号：US20100135417A1
公开(公告)日：2010-06-03
申请号：US12326654
申请日：2008-12-02
申请人： Asaf Hargil
发明人： Asaf Hargil
IPC分类号： H04N11/02 , H04N11/04
CPC分类号： H04N19/85 , H04N19/117 , H04N19/156 , H04N19/42
摘要： A video processing device may comprise a video processing logic to control the enhancement operations performed on the video processing device. The video processing logic may determine a short term frame rate average value in response to receiving a plurality of video frames. Further, the video processing logic may generate a derivative of the short term frame rate using the short term frame rate value. The video processing logic may then activate monitoring of a processor usage if the derivative of the short term frame rate is below a first threshold value. The video processing logic may then reduce the performance of rendering of the plurality of video frames if a processor usage average value is above a second threshold. While restoring the performance, the video processing logic may restore the enhancement operations in steps after determining that processor resources are available.
摘要翻译：视频处理设备可以包括视频处理逻辑以控制对视频处理设备执行的增强操作。响应于接收多个视频帧，视频处理逻辑可以确定短期帧速率平均值。此外，视频处理逻辑可以使用短期帧速率值来生成短期帧频的导数。如果短期帧速率的导数低于第一阈值，则视频处理逻辑可以激活处理器使用的监视。如果处理器使用平均值高于第二阈值，则视频处理逻辑可以降低多个视频帧的渲染性能。在还原性能的同时，视频处理逻辑可以在确定处理器资源可用之后逐步恢复增强操作。

7. 发明申请

US20100115014A1 Instruction and logic for performing range detection 有权
标题翻译：用于执行范围检测的指令和逻辑
公开(公告)号：US20100115014A1
公开(公告)日：2010-05-06
申请号：US12290565
申请日：2008-10-31
申请人： Asaf Hargil , Evgeny Fiksman , Artiom Myaskouvskey , Doron Orenstien
发明人： Asaf Hargil , Evgeny Fiksman , Artiom Myaskouvskey , Doron Orenstien
IPC分类号： G06F7/02 , G06F17/17 , G06F17/16
CPC分类号： G06F17/17 , G06F9/30003
摘要： A technique to accelerate range detection in a spline calcuation. In one embodiment, an instruction and corresponding logic are provided to perform range detection within a computer or processor.
摘要翻译：一种在样条计算中加速范围检测的技术。在一个实施例中，提供指令和相应的逻辑以在计算机或处理器内执行范围检测。

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