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1. 发明授权

US08793657B2 Visual debugger for dynamic XSL transformations 有权
标题翻译：用于动态XSL转换的可视化调试器
公开(公告)号：US08793657B2
公开(公告)日：2014-07-29
申请号：US11284172
申请日：2005-11-21
申请人： Ella Belisario , Gordon R. Chiu , Erin Harris , Christina P. Lau , Peter A. Nicholls , Ilene R. Seelemann , Henry Zongaro
发明人： Ella Belisario , Gordon R. Chiu , Erin Harris , Christina P. Lau , Peter A. Nicholls , Ilene R. Seelemann , Henry Zongaro
IPC分类号： G06F9/44
CPC分类号： G06F11/362
摘要： The present invention provides a visual debugger for dynamic XLS transformations. A method for real time debugging of mixed Java and Extensible Stylesheet Language Transform (XSLT) code comprises sending debug events from Java and XSLT debug sub-adapters to a debug super adapter, filtering the debug events received from the Java and XSLT debug sub-adapters, generating debug events representing a consolidated view of the received debug events, and sending the debug events to a debug user interface (UI).
摘要翻译：本发明提供了用于动态XLS变换的可视调试器。混合Java和可扩展样式表语言转换（XSLT）代码的实时调试方法包括将调试事件从Java和XSLT调试子适配器发送到调试超级适配器，过滤从Java和XSLT调试子适配器接收的调试事件生成表示接收到的调试事件的统一视图的调试事件，以及将调试事件发送到调试用户界面（UI）。

2. 发明授权

US07412677B1 Detecting reducible registers 有权
标题翻译：检测可还原寄存器
公开(公告)号：US07412677B1
公开(公告)日：2008-08-12
申请号：US11360739
申请日：2006-02-22
申请人： Valavan Manohararajah , Gordon R. Chiu , Deshanand Singh , Stephen Brown
发明人： Valavan Manohararajah , Gordon R. Chiu , Deshanand Singh , Stephen Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/504 , G06F2217/84
摘要： Reducible registers are determined to optimize a sequential circuit. A screening method tests one or more sets of registers where the registers of each set are assumed to satisfy a logic condition. The tests determine if the logic condition holds. If the logic condition of a set is found to be violated, the registers may be moved to another set having a different logic condition or removed completely. The registers remaining are potentially reducible. The reducibility of the registers is verified via Boolean analysis by verifying the logic conditions of a register set for each register. If a register does not pass verification, it then may be moved to a different set having a different logic condition or removed completely. The sets that pass verification are reducible.
摘要翻译：确定可减少寄存器以优化顺序电路。一种筛选方法测试一组或多组寄存器，其中假设每个寄存器的寄存器满足逻辑条件。测试确定逻辑条件是否成立。如果发现集合的逻辑条件被违反，则可以将寄存器移动到具有不同逻辑条件的另一集合或完全移除。剩余的寄存器是可以减少的。通过布尔分析来验证寄存器的可复原性，通过验证每个寄存器的寄存器集的逻辑条件。如果寄存器不通过验证，则可以将其移动到具有不同逻辑条件的不同集合或完全移除。通过验证的集合是可以减少的。

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