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1. 发明授权

US06208211B1 Low jitter phase locked loop having a sigma delta modulator and a method thereof 有权
标题翻译：具有Σ-Δ调制器的低抖动锁相环及其方法
公开(公告)号：US06208211B1
公开(公告)日：2001-03-27
申请号：US09406014
申请日：1999-09-24
申请人： Eliav Zipper , Michael Zarubinsky , David Moshe , Yachin Afek
发明人： Eliav Zipper , Michael Zarubinsky , David Moshe , Yachin Afek
IPC分类号： H03B502
CPC分类号： H03L7/093 , H03L7/085 , H03L7/0995 , H03L7/18
摘要： A phase locked loop PLL has a current controlled oscillator ICO, having an input resistance Rin. Rin is proportional to a control current Idac sent to ICO. ICO is coupled to a capacitor, the capacitor and Rin introduce a pole Fpole in the transfer function of PLL. The PLL further has a sigma delta modulator, for providing a digital sigma delta modulated control signal SDO, SDO is converted to an analog control current Idac, that is provided to ICO and smoothed by Rin and the capacitor. The sigma delta modulator forces error signal outside a predetermined frequency BWsd; and Fpole tracks BWsd.
摘要翻译：锁相环PLL具有电流控制振荡器ICO，具有输入电阻Rin。 Rin与发送到ICO的控制电流Idac成正比。 ICO耦合到一个电容器，电容和Rin引入一个极点Fpole在PLL的传递函数。 PLL还具有Σ-Δ调制器，用于提供数字Σ-Δ调制控制信号SDO，将SDO转换为提供给ICO并由Rin和电容器平滑的模拟控制电流Idac。 Σ-Δ调制器将误差信号强制在预定频率BWsd之外; 和Fpole轨道BWsd。

2. 发明授权

US06570947B1 Phase lock loop having a robust bandwidth and a calibration method thereof 有权
标题翻译：具有鲁棒带宽的锁相环及其校准方法
公开(公告)号：US06570947B1
公开(公告)日：2003-05-27
申请号：US09404933
申请日：1999-09-24
申请人： Eliav Zipper , Michael Zarubinsky , Yachin Afek
发明人： Eliav Zipper , Michael Zarubinsky , Yachin Afek
IPC分类号： H03D324
CPC分类号： H03L7/093 , H03L7/107 , H03L7/18
摘要： A phase lock loop having an bandwidth that does not depend upon N. The phase lock loop comprising: a controlled oscillator, a frequency divider by N, a phase detector for producing an error signal ER, and an adjustable converter, coupled to the phase detector and to the current controlled oscillator, for receiving ER and providing the controlled oscillator a control signal such that that the (Fico/N) ranges between a minimum value of Fmin and a maximal value of Fmax, wherein Fref=(Fmin+Fmax)/2.
摘要翻译：具有不依赖于N的带宽的锁相环。锁相环包括：受控振荡器，N分频器，用于产生误差信号ER的相位检测器和可调整转换器，耦合到相位检测器以及当前受控振荡器，用于接收ER并向控制振荡器提供控制信号，使得（Fico / N）范围在最小值Fmin和最大值Fmax之间，其中Fref =（Fmin + Fmax）/ 2。

3. 发明授权

US5889482A Analog-to-digital converter using dither and method for converting analog signals to digital signals 失效
标题翻译：使用抖动的模数转换器和将模拟信号转换为数字信号的方法
公开(公告)号：US5889482A
公开(公告)日：1999-03-30
申请号：US944639
申请日：1997-10-06
申请人： Michael Zarubinsky , Yachin Afek , Vladimir Koifman
发明人： Michael Zarubinsky , Yachin Afek , Vladimir Koifman
IPC分类号： H03M3/02 , H03M1/20
CPC分类号： H03M3/33 , H03M3/458
摘要： An analog-to-digital converter (100) has a first path (110) with a first sigma-delta modulator (114) which transforms an analog input signal X.sub.0 (111') from an input terminal (101) to a digital output signal Y.sub.0 at an output terminal (102). In a second path (120), a digital dither signal D (121') is combined with a digital intermediate signal Z.sub.0 (115') from the first modulator (114) and digitally processed by a second sigma-delta modulator (124) to an intermediate signal Y.sub.1 (125') Y.sub.1 is fed to the first modulator (114) and to the output terminal (102) with opposite sign ("+" and "-", respectively). Thereby, multipliers (133 and 127) attenuate Y.sub.1. The dither signal D (121') is used substantially only within the converter (100), and is substantially canceled before the output terminal (102). This features preserve a high SNR of the converter (100) and low spectral tones in output signal Y.sub.0.
摘要翻译：模拟 - 数字转换器（100）具有第一路径（110），其具有将来自输入端（101）的模拟输入信号X0（111'）变换成数字输出信号的第一Σ-Δ调制器（114） Y0在输出端子（102）处。在第二路径（120）中，将数字抖动信号D（121'）与来自第一调制器（114）的数字中间信号Z0（115'）组合并由第二Σ-Δ调制器（124）进行数字处理，中间信号Y1（125'）Y1以相反的符号（分别为“+”和“ - ”）馈送到第一调制器（114）和输出端子（102）。由此，乘法器（133和127）衰减Y1。抖动信号D（121'）基本上仅在转换器（100）内使用，并且在输出端（102）之前基本上被消除。这特征保留了转换器（100）的高SNR和输出信号Y0中的低频谱。

4. 发明授权

US06313774B1 Delta-sigma analog-to-digital converter, and method 有权
标题翻译： Delta-sigma模数转换器和方法
公开(公告)号：US06313774B1
公开(公告)日：2001-11-06
申请号：US09574022
申请日：2000-05-19
申请人： Michael Zarubinsky , Yachin Afek
发明人： Michael Zarubinsky , Yachin Afek
IPC分类号： H03M300
CPC分类号： H03M3/412
摘要： An analog-to-digital converter (200) has a first stage (207) to integrate and quantize the difference between a feedback signal (R) and an input signal (X) to a first intermediate signal (Y1) with a first resolution (M1), a second stage (208) to integrate and quantize the first intermediate signal (Y1) to a second intermediate signal (Y2) with a second, lower resolution (M2), a feedback stage (260) to convert the second intermediate signal (Y2) to the feedback signal (R), and a third stage (206, 270, 280, 285) to differentiate the first intermediate signal (Y1) to a third intermediate signal (W1), to delay the second intermediate signal (Y2) to a fourth intermediate signal (W2), and to add the third and fourth intermediate signals (W1, W2) to an output signal (Y) having a resolution that results from the sum of the first (M1) and second (M2) resolutions.
摘要翻译：模数转换器（200）具有第一级（207），以将第一中间信号（Y1）的反馈信号（R）和输入信号（X）之间的差积分和量化为具有第一分辨率（ M1），第二级（208），用于将第一中间信号（Y1）积分和量化为具有第二较低分辨率（M2）的第二中间信号（Y2），反馈级（260）将第二中间信号（Y2）到反馈信号（R），以及第三级（206,270,280,285），以将第一中间信号（Y1）区分为第三中间信号（W1），以延迟第二中间信号（Y2 ）到第四中间信号（W2），并且将第三和第四中间信号（W1，W2）加到具有由第一（M1）和第二（M2）的和产生的分辨率的输出信号（Y）决议。

5. 发明授权

US6028544A Digital-to-analog converter with noiseshaping modulator, commutator and plurality of unit converters, and method 失效
标题翻译：具有噪声调制器，换向器和多个单位转换器的数模转换器及方法
公开(公告)号：US6028544A
公开(公告)日：2000-02-22
申请号：US002421
申请日：1998-01-02
申请人： Michael Zarubinsky , Vladimir Koifman , Yachin Afek
发明人： Michael Zarubinsky , Vladimir Koifman , Yachin Afek
IPC分类号： H03M3/02 , H03M3/04 , H03M7/00 , H03M3/00
CPC分类号： H03M3/326 , H03M3/502 , H03M7/3026 , H03M7/304
摘要： A digital-to-analog converter (200) has a first portion (208) which receives a digital input signal X (201') and has serially coupled a second portion (209) which provides an analog output signal Y (202'). The first portion (208) is a delta-sigma modulator with integrators (210 and 215), adders (203 and 205), a comparator (220) and delay stages (230 and 235). The second portion (209) comprises a commutator (260), unit converters (280-n) and an analog adder (290). In the second portion, the unit converters (280-n) can be mismatched. The first portion (208) provides a noise-shaped intermediate signal V (221') which has substantially zero noise at that frequencies where the mismatches would lead to unwanted spectral tones.
摘要翻译：数模转换器（200）具有接收数字输入信号X（201'）的第一部分（208），并且串联地耦合提供模拟输出信号Y（202'）的第二部分（209）。第一部分（208）是具有积分器（210和215），加法器（203和205），比较器（220）和延迟级（230和235）的Δ-Σ调制器。第二部分（209）包括换向器（260），单位转换器（280-n）和模拟加法器（290）。在第二部分中，单位转换器（280-n）可能不匹配。第一部分（208）提供噪声形状的中间信号V（221'），该中间信号V（221'）在失配将导致不想要的频谱的频率处具有基本上为零的噪声。

6. 发明授权

US06380811B1 Signal generator, and method 有权
标题翻译：信号发生器和方法
公开(公告)号：US06380811B1
公开(公告)日：2002-04-30
申请号：US09784279
申请日：2001-02-16
申请人： Michael Zarubinsky , Konstantin Berman , Eliav Zipper
发明人： Michael Zarubinsky , Konstantin Berman , Eliav Zipper
IPC分类号： H03L706
CPC分类号： H03L7/0993 , H03L7/085 , H03L7/23
摘要： A signal generator (100) receives an input clock signal (X1) at a first frequency (F1) and derives an output clock signal (Y) at a second frequency (FY). An arrangement (110) using a first intermediate signal (Z) receives the input clock signal (X1) and provides a second intermediate signal (X2) by selectively providing transitions (119) of the second intermediate signal (X2) at time intervals (T2(n)) that are determined by a variable number (A+P(n)) of periods (TZ) of the first intermediate signal (Z). The second intermediate signal (X2) has a frequency (F2) that is in average (F′2) higher than the first frequency (F1). A phase-looked loop (PLL) circuit (180) locks at this average frequency (F′2) and provides the output clock signal (Y).
摘要翻译：信号发生器（100）以第一频率（F1）接收输入时钟信号（X1），并以第二频率（FY）导出输出时钟信号（Y）。使用第一中间信号（Z）的装置（110）通过选择性地以时间间隔（T2）提供第二中间信号（X2）的转变（119）来接收输入时钟信号（X1）并提供第二中间信号（X2）（N）），其由第一中间信号（Z）的周期（TZ）的可变数（A + P（n））确定。第二中间信号（X2）具有比第一频率（F1）高的平均值（F'2）的频率（F2）。相位环路（PLL）电路（180）以该平均频率（F'2）锁定并提供输出时钟信号（Y）。

7. 发明授权

US06181168B2 High speed phase detector and a method for detecting phase difference 有权
标题翻译：高速相位检测器和相位差检测方法
公开(公告)号：US06181168B2
公开(公告)日：2001-01-30
申请号：US09405191
申请日：1999-09-24
申请人： Michael Zarubinsky , Eliav Zipper , Leonid Tsukerman
发明人： Michael Zarubinsky , Eliav Zipper , Leonid Tsukerman
IPC分类号： H03D1300
CPC分类号： H03D13/002
摘要： A phase detector and a method for detecting phase difference between two high frequency signals, the phase detector is adapted to receive a reference signal REF, a high frequency signal ICOS, and a signal FD synchronized to ICOS. REF, ICOS and FD have opposite edges. The phase detector comprising of: An asynchronous phase detector circuit, for providing an asynchronous control signal CTP, for representing a time interval between a time of occurrence of an edge of REF and the time of occurrence of a corresponding edge of ICOS. A synchronous phase detector circuit, for providing an synchronous control signal TC, for representing a time interval between a time of the occurrence of the corresponding edge of ICOS and the time of occurrence of a corresponding edge of FD.A combing circuit, for receiving TC and CTP and providing an error signal ERS, representing the phase difference between REF and FD.
摘要翻译：相位检测器和用于检测两个高频信号之间的相位差的方法，相位检测器适于接收参考信号REF，高频信号ICOS和与ICOS同步的信号FD。 REF，ICOS和FD有相反的边。相位检测器包括：用于提供异步控制信号CTP的异步相位检测器电路，用于表示REF的边缘出现时间与ICOS的对应边缘出现时间之间的时间间隔。一种用于提供同步控制信号TC的同步相位检测器电路，用于表示ICOS的相应边缘出现的时间与FD的相应边缘的发生时间之间的时间间隔。一个组合电路，用于接收TC 和CTP，并提供表示REF和FD之间的相位差的误差信号ERS。

8. 发明申请

US20140133552A1 METHOD AND APPARATUS FOR ENCODING AN IMAGE 有权
标题翻译：用于编码图像的方法和装置
公开(公告)号：US20140133552A1
公开(公告)日：2014-05-15
申请号：US14131368
申请日：2011-07-20
申请人： Shlomo Beer-Gingold , Ofer Naaman , Michael Zarubinsky
发明人： Shlomo Beer-Gingold , Ofer Naaman , Michael Zarubinsky
IPC分类号： H04N19/635 , H04N19/13 , H04N19/136 , H04N19/51 , H04N19/169
CPC分类号： H04N19/426 , H04N19/13 , H04N19/136 , H04N19/1883 , H04N19/513 , H04N19/63 , H04N19/635 , H04N19/93
摘要： A method for processing an image, the method comprising retrieving an image, encoding the image as a string of components, deriving an exponent for each component, deriving mantissas wherein at least an approximation of each component can be derived from the exponents and mantissas, and wherein each exponent indicates the number of bits in its accompanying mantissa, compressing at least the exponents, and storing the exponents and the mantissas in a memory. There is also provided a apparatus for processing an image.
摘要翻译：一种用于处理图像的方法，所述方法包括检索图像，将图像编码为一组分量，导出每个分量的指数，导出尾数，其中至少可以从指数和尾数导出每个分量的近似，以及其中每个指数指示其伴随尾数中的位数，至少压缩指数，并将指数和尾数存储在存储器中。还提供了一种用于处理图像的装置。

9. 发明申请

US20110013088A1 DEVICE AND METHOD FOR EVALUATING CONNECTIVITY BETWEEN A VIDEO DRIVER AND A DISPLAY 有权
标题翻译：用于评估视频驱动器和显示器之间的连接性的装置和方法
公开(公告)号：US20110013088A1
公开(公告)日：2011-01-20
申请号：US12933243
申请日：2008-04-11
申请人： Anton Rozen , Shlomo Beer-Gingold , Michael Zarubinsky
发明人： Anton Rozen , Shlomo Beer-Gingold , Michael Zarubinsky
IPC分类号： H04N5/14
CPC分类号： G09G5/006 , G09G3/006 , G09G2330/12 , G09G2370/04 , H04N17/04
摘要： A device for evaluating connectivity between a video driver and a display, the device comprises a first video driver, a first output connector, a first terminating resistance; wherein the device is characterized by comprising a first comparison unit; wherein the first video driver has an output port that is coupled to the first output connector, to the first terminating resistance and to the first comparison unit; wherein the first output connector is configured to be coupled via a first cable to a first input of the display; wherein the first comparison unit is adapted to perform comparisons between a voltage level on the first terminating resistance to multiple thresholds and to determine whether a display first input impedance is substantially equal to the first terminating resistance, whether the display first input impedance is substantially lower then the first terminating resistance, or whether the first video driver is disconnected from the display; wherein the comparisons are executed during a pixel information idle period.
摘要翻译：一种用于评估视频驱动器和显示器之间的连接性的装置，所述装置包括第一视频驱动器，第一输出连接器，第一终端电阻器，其中所述装置的特征在于包括第一比较单元; 其中所述第一视频驱动器具有耦合到所述第一输出连接器，所述第一终端电阻和所述第一比较单元的输出端口; 其中所述第一输出连接器被配置为经由第一电缆耦合到所述显示器的第一输入; 其中所述第一比较单元适于执行所述第一终端电阻与多个阈值之间的电压电平的比较，并且确定显示器第一输入阻抗是否基本上等于所述第一终端电阻，所述显示器第一输入阻抗是否显着低于所述第一终端电阻第一终端电阻，或第一视频驱动器是否与显示器断开连接; 其中比较在像素信息空闲期间执行。

10. 发明申请

US20080253694A1 Method and Device for Processing Image Data Stored in a Frame Buffer 有权
标题翻译：用于处理存储在帧缓冲器中的图像数据的方法和设备
公开(公告)号：US20080253694A1
公开(公告)日：2008-10-16
申请号：US11914873
申请日：2005-05-23
申请人： Konstantin Berman , Michael Zarubinsky
发明人： Konstantin Berman , Michael Zarubinsky
IPC分类号： G06K9/60
CPC分类号： G06T1/20 , G09G5/39 , G09G5/399 , G09G2360/123
摘要： A device and method for data image processing. The method includes writing, image data to a certain buffer by an image data provider; characterized by repeating steps of reading, by an image processor image data from a first entry of a certain buffer, processing the image data by the image processor, and writing processed image data to a second entry of the certain buffer; wherein the repeating ends when at least two memory pages of the certain buffer are read; wherein a distance between the first and second entries is smaller than a size of a page of the certain buffer and conveniently much smaller than the size of the page; wherein the second entry includes image data that was previously read by the image processor during the certain period; and preventing an image data provider and an image data retriever form accessing the certain buffer during the repetition.
摘要翻译：一种用于数据图像处理的设备和方法。该方法包括由图像数据提供者将图像数据写入特定缓冲器; 其特征在于重复以下步骤：通过图像处理器从特定缓冲器的第一条目读取图像数据，由图像处理器处理图像数据，并将处理后的图像数据写入特定缓冲器的第二条目; 其中当所述特定缓冲器的至少两个存储器页被读取时，所述重复结束; 其中所述第一和第二条目之间的距离小于所述特定缓冲器的页面的大小，并且方便地远小于所述页面的大小; 其中所述第二条目包括在所述特定时段期间由所述图像处理器先前读取的图像数据; 并且在重复期间防止图像数据提供者和图像数据检索器形成访问某个缓冲器。

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