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    • 10. 发明授权
    • Semiconductor device and method for designing same
    • 半导体装置及其设计方法
    • US07723848B2
    • 2010-05-25
    • US11522436
    • 2006-09-18
    • Hiroki Matsumoto
    • Hiroki Matsumoto
    • H01L23/48
    • H01L23/5226H01L21/76838H01L2924/0002H01L2924/00
    • A silica residue is generated, due to a presence of a step formed by a presence of the first layer metallic interconnect, and then, the residual silica is etched to form hollow portions when vias for the metallic interconnect provided in a layer above thereof is formed, and further, insulating materials remained above the hollow portions flakes off to create contaminants, leading to a reduction in the production yield. In the present invention, interconnects provided in a layer underlying a via group, which are provided for coupling to the upper layer interconnect layer, are disposed so as to cover vias composing its via group.
    • 由于存在通过存在第一层金属互连形成的台阶,产生二氧化硅残余物,然后,当形成在其上方的金属互连件的通孔形成通孔时,残留的二氧化硅被蚀刻以形成中空部分 此外,保留在中空部分上方的绝缘材料剥落以产生污染物,导致生产产量的降低。 在本发明中,设置在与上层互连层连接的通孔组下面的层中的互连布置成覆盖构成其通孔组的通孔。