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1. 发明授权

US07233889B2 Method, apparatus, and computer program for evaluating noise immunity of a semiconductor device 有权
标题翻译：用于评估半导体器件的抗噪声性的方法，装置和计算机程序
公开(公告)号：US07233889B2
公开(公告)日：2007-06-19
申请号：US10278507
申请日：2002-10-23
申请人： Eiji Takahashi , Yoshiyuki Saito , Yukihiro Fukumoto , Hiroshi Benno
发明人： Eiji Takahashi , Yoshiyuki Saito , Yukihiro Fukumoto , Hiroshi Benno
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of evaluating noise immunity of a semiconductor device is provided. An actual circuit including the semiconductor device is represented by an equivalent circuit which has a target equivalent circuit, a noise source equivalent circuit, and an external equivalent circuit connected in parallel. The target equivalent circuit represents the semiconductor device. The noise source equivalent circuit represents a noise source outside the semiconductor device, and supplies noise to the target equivalent circuit. The external equivalent circuit represents a circuit outside the semiconductor device. The noise immunity is evaluated based on a voltage or current which arises in the target equivalent circuit by the noise. In this way, the immunity of the semiconductor device against extraneous noise can be evaluated in consideration of the effects of the circuitry outside the semiconductor device.
摘要翻译：提供了一种评估半导体器件的抗噪声性的方法。包括半导体器件的实际电路由具有并联连接的目标等效电路，噪声源等效电路和外部等效电路的等效电路表示。目标等效电路表示半导体器件。噪声源等效电路表示半导体器件外部的噪声源，并且将噪声提供给目标等效电路。外部等效电路表示半导体器件外部的电路。基于由噪声在目标等效电路中产生的电压或电流来评估噪声抗扰度。以这种方式，可以考虑半导体器件外的电路的影响来评估半导体器件对外来噪声的抗扰性。

2. 发明授权

US06901343B2 MULTILAYER BOARD IN WHICH WIRING OF SIGNAL LINE THAT REQUIRES TAMPER-RESISTANCE IS COVERED BY COMPONENT OR FOIL, DESIGN APPARATUS, METHOD, AND PROGRAM FOR THE MULTILAYER BOARD, AND MEDIUM RECORDING THE PROGRAM 有权
标题翻译：组件或者硬盘所要求的防篡改信号线的多层板，多层板的设计，方法和程序，以及程序的中程记录
公开(公告)号：US06901343B2
公开(公告)日：2005-05-31
申请号：US10029571
申请日：2001-12-20
申请人： Eiji Takahashi , Yukihiro Fukumoto , Yoshiyuki Saito , Osamu Shibata , Shinichi Tanimoto , Takeshi Nakayama
发明人： Eiji Takahashi , Yukihiro Fukumoto , Yoshiyuki Saito , Osamu Shibata , Shinichi Tanimoto , Takeshi Nakayama
IPC分类号： G06F17/50 , H05K1/00 , H05K1/02 , H05K1/11 , H04L9/32
CPC分类号： G06F17/5068 , H05K1/0275 , H05K1/0298 , H05K1/114 , H05K2201/09627 , H05K2201/09772 , H05K2201/10151
摘要： A signal line, being in a six-layer board and connecting terminal 102 of component 101 with terminal 115 of component 114, requires tamper-resistance. The signal line is composed of foil 103 on an outside layer, a via 104, foil 111 on the third layer, via 105, foil 112 on the fourth layer, via 106, and foil 113 on the sixth layer. Portions of the signal line that exist on outside layers are all hidden under circuit components. Foil 103 and an end of via 104 are placed under component 101 on first layer 116, an end of via 105 is placed under component 107 on layer 116, an end of via 106 is placed under component 108 on layer 116, the other end of via 104 is placed under component 109 on sixth layer 121, the other end of via 105 is placed under component 110 on layer 121, and foil 113 and the other end of via 106 are placed under component 114 on layer 121.
摘要翻译：在组件101的六层板和连接端子102与元件114的端子115之间的信号线需要防篡改。信号线由外层的箔103，通孔104，第三层上的箔111，通孔105，第四层上的箔112，第106层和第六层上的箔113组成。存在于外层的信号线部分都隐藏在电路元件下面。箔103和通孔104的末端放置在第一层116上的部件101下方，通孔105的端部放置在层116上的部件107的下方，通孔106的端部放置在层116上的部件108的下方，另一端通孔104被放置在第六层121上的部件109的下方，通孔105的另一端被放置在层121上的部件110下方，并且箔113和通孔106的另一端放置在层121上的部件114下方。

3. 发明授权

US06812741B2 Bidirectional signal transmission circuit and bus system 失效
标题翻译：双向信号传输电路和总线系统
公开(公告)号：US06812741B2
公开(公告)日：2004-11-02
申请号：US10394677
申请日：2003-03-21
申请人： Osamu Shibata , Yoshiyuki Saito , Yukihiro Fukumoto
发明人： Osamu Shibata , Yoshiyuki Saito , Yukihiro Fukumoto
IPC分类号： H03K190175
CPC分类号： H04L25/0292 , G06F13/4086 , H04L5/16 , H04L25/0278 , H04L25/028
摘要： A bidirectional transmission circuit for inputting/outputting a signal from/onto a bidirectional transmission line includes: a transceiver for transmitting/receiving a signal; a first element having an impedance; a second element being a short line; and a switching unit for coupling the transceiver to the bidirectional transmission line via the first element when the transceiver transmits a signal, and coupling the transceiver to the bidirectional transmission line via the second element when the transceiver receives a signal.
摘要翻译：用于从双向传输线路输入/输出信号的双向传输电路包括：用于发送/接收信号的收发器; 具有阻抗的第一元件; 第二个元素是短线; 以及切换单元，用于当收发器发送信号时，经由第一元件将收发器耦合到双向传输线，并且当收发器接收到信号时，将收发器经由第二元件耦合到双向传输线。

4. 发明申请

US20090290274A1 REMOVABLE MEMORY CARD 审中-公开
标题翻译：可拆卸记忆卡
公开(公告)号：US20090290274A1
公开(公告)日：2009-11-26
申请号：US12468475
申请日：2009-05-19
申请人： Hiroshi SUENAGA , Yoshiyuki Saito , Osamu Shibata , Yukihiro Fukumoto
发明人： Hiroshi SUENAGA , Yoshiyuki Saito , Osamu Shibata , Yukihiro Fukumoto
IPC分类号： H02H9/04 , H05K1/02
CPC分类号： G06K19/07743 , G06K19/07732 , G06K19/07735 , H01L2224/16225 , H05K1/0237 , H05K1/0259 , H05K1/112 , H05K1/117 , H05K2201/094 , H05K2201/09736 , H05K2201/09845 , H05K2201/10159 , H05K2201/10174 , H05K2201/10674
摘要： According to the present invention, the setting height position of a first terminal is set to be lower than the setting height position of a second terminal on the terminal formation surface of a printed substrate, so that the protection of an internal circuit and the transmission of a high-speed signal can be both achieved.
摘要翻译：根据本发明，第一端子的设定高度位置被设定为低于印刷基板的端子形成面上的第二端子的设定高度位置，使得内部电路的保护和传输可以实现高速信号。

5. 发明授权

US06691296B1 Circuit board design aiding 失效
标题翻译：电路板设计辅助
公开(公告)号：US06691296B1
公开(公告)日：2004-02-10
申请号：US09241946
申请日：1999-02-01
申请人： Takeshi Nakayama , Yukihiro Fukumoto , Yoshiyuki Saito , Hirokazu Uemura
发明人： Takeshi Nakayama , Yukihiro Fukumoto , Yoshiyuki Saito , Hirokazu Uemura
IPC分类号： G06F1750
CPC分类号： H05K3/0005 , G06F17/5036 , G06F17/5072 , G06F17/5077 , H01L2924/15192 , H05K1/0231 , H05K1/0298 , H05K1/115 , H05K2201/10689
摘要： A net detecting unit detects a set of component terminal interconnection information showing a critical net from a component terminal interconnection information list. A conductor detecting unit detects a conductor corresponding to the critical net. A component detecting unit detects two components from the set of component terminal interconnection information. A terminal detecting unit detects a power and/or ground terminal of each of the detected components. A power/ground layer detecting unit detects at least one layer, among power and ground layers, to which the detected power and/or ground terminals are connected. A layer detecting unit specifies a layer, among the detected layers, that is nearest to a signal layer on which the conductor is placed. A prohibition area generating unit generates a via prohibition area on the specified layer. As a result, vias are placed on the specified layer, avoiding the via prohibition area.
摘要翻译：网络检测单元从组件终端互连信息列表检测表示关键网络的一组组件终端互连信息。导体检测单元检测与关键网相对应的导体。分量检测单元从组件端子互连信息的集合中检测两个分量。终端检测单元检测每个检测到的组件的功率和/或接地端子。电源/接地层检测单元检测所连接的检测到的电力和/或接地端子的功率和接地层中的至少一层。层检测单元指定在所检测的层之中最接近放置导体的信号层的层。禁止区域生成单元在指定的层上生成通路禁止区域。结果，通孔被放置在指定的层上，避免了通孔禁止区域。

6. 发明授权

US06629302B2 Circuit board design aiding apparatus, design aiding method, and storage medium storing design aiding program 有权
标题翻译：电路板设计辅助设备，设计辅助方法和存储设备辅助程序存储介质
公开(公告)号：US06629302B2
公开(公告)日：2003-09-30
申请号：US09746886
申请日：2000-12-22
申请人： Shinji Miura , Yukihiro Fukumoto , Hirokazu Uemura , Yoshiyuki Saito , Hiroshi Ikeda , Takeshi Nakayama , Osamu Shibata , Shinichi Tanimoto
发明人： Shinji Miura , Yukihiro Fukumoto , Hirokazu Uemura , Yoshiyuki Saito , Hiroshi Ikeda , Takeshi Nakayama , Osamu Shibata , Shinichi Tanimoto
IPC分类号： G06F945
CPC分类号： G06F17/5068
摘要： A design aiding apparatus and a method, and a storage medium storing a design aiding program enable the efficient layout design of components in a multilayer wiring board formed by laminating a plurality of wiring layers. The design aiding apparatus includes (a) a first acquiring unit for acquiring information showing a first location in a lamination direction of the wiring layers, (b) a second acquiring unit for acquiring information showing a second location on a two-dimensional plane that is orthogonal to the lamination direction, and (c) a placement unit for generating information showing a space to be occupied when the component is placed in such a manner that a placement reference point of the component coincides with the second location that is on the two-dimensional plane including the first location. According to the above construction, the present invention is capable of aiding layout design of components in the wiring board.
摘要翻译：设计辅助装置和方法以及存储设计辅助程序的存储介质使得能够通过层叠多个布线层而形成的多层布线板中的部件的有效布局设计。设计辅助装置包括：（a）第一获取单元，用于获取表示布线层的层叠方向上的第一位置的信息，（b）第二获取单元，用于获取表示二维平面上的第二位置的信息，与所述层叠方向正交，以及（c）放置单元，用于产生表示当所述部件以所述部件的放置基准点与所述第二位置的所述第二位置一致的方式配置时要占据的空间的信息，包括第一位置的三维平面。根据上述结构，本发明能够帮助布线板中部件的布局设计。

7. 发明申请

US20090097301A1 SEMICONDUCTOR STORAGE APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT INCORPORATING THE SAME 审中-公开
标题翻译：半导体存储器件和半导体集成电路并入其中
公开(公告)号：US20090097301A1
公开(公告)日：2009-04-16
申请号：US11915816
申请日：2006-05-18
申请人： Eiji Takahashi , Yoshiyuki Saito
发明人： Eiji Takahashi , Yoshiyuki Saito
IPC分类号： G11C11/24 , G11C7/00
CPC分类号： H01L27/101 , G11C11/404 , G11C11/4074 , G11C11/4076 , H01L27/1085 , H01L27/10882
摘要： An object is to provide a semiconductor memory device which can dynamically change the number of memory cells used as by-pass capacitors. In each memory block, one selector signal line is provided in parallel to one word line. In a pair of the word line and the selector signal line adjacent to each other, states are maintained opposite to each other. Further, in a memory block, one branch of a supply line is provided in parallel to one bit line. In each of the memory cells, a first transistor connects a capacitor to the bit line in accordance with the state of the word line. Furthermore, a second transistor connects the same capacitor to the branch of the supply line in accordance with the state of the selector signal line. In the memory cells aligned in a row direction, gates of the first transistors are connected to the same word line, and gates of the second transistors are connected to the same selector signal line.
摘要翻译：本发明的目的是提供一种半导体存储器件，其可以动态地改变用作旁路电容器的存储单元的数量。在每个存储块中，一条选择器信号线与一条字线平行地提供。在彼此相邻的一对字线和选择器信号线中，状态保持彼此相对。此外，在存储块中，供给线的一个分支与一个位线并行设置。在每个存储单元中，第一晶体管根据字线的状态将电容器连接到位线。此外，第二晶体管根据选择器信号线的状态将相同的电容器连接到电源线的分支。在沿行方向排列的存储单元中，第一晶体管的栅极连接到相同的字线，第二晶体管的栅极连接到相同的选择信号线。

8. 发明申请

US20050289269A1 Slave device, master device and stacked device 有权
标题翻译：从设备，主设备和堆叠设备
公开(公告)号：US20050289269A1
公开(公告)日：2005-12-29
申请号：US11149171
申请日：2005-06-10
申请人： Takeshi Nakayama , Eiji Takahashi , Yoshiyuki Saito , Yukihiro Ishimaru , Hideki Iwaki
发明人： Takeshi Nakayama , Eiji Takahashi , Yoshiyuki Saito , Yukihiro Ishimaru , Hideki Iwaki
IPC分类号： G06F13/00 , G06F13/40 , G06F13/42
CPC分类号： G06F13/409 , G06F13/4226 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/16145 , H01L2924/00014 , H01L2224/05599 , H01L2224/05099
摘要： A stacked device is disclosed which is easily manufactured while identifying a plurality of devices that are stacked in the stacked device. The stacked device includes a stack of a plurality of slave devices and a master device having identical terminal arrangements. Here, the master device includes command transmission unit configured to input an identification command to a terminal of an adjacent slave device. Furthermore, the slave device includes a through-wire for interconnecting at least one terminal of that same device and an adjacent slave device; command reception unit configured to receive the identification command; and ID (identifier) setting unit configured to set the ID of that same device based on the identification command; the positions of the terminals that are interconnected with the adjacent slave devices differing in each slave device, so that, in each slave device, the slave device command reception unit receive an identification command having a modified value as a result of transiting through-wires that are connected at differing positions in each slave device.
摘要翻译：公开了一种容易制造的堆叠式装置，同时识别堆叠在堆叠装置中的多个装置。堆叠式装置包括多个从装置的堆叠和具有相同端子装置的主装置。这里，主设备包括命令传输单元，其被配置为向相邻从设备的终端输入识别命令。此外，从设备包括用于互连同一设备的至少一个终端和相邻从设备的通线; 命令接收单元，被配置为接收所述识别命令; ID（识别符）设定部，其基于所述识别命令来设定同一设备的ID; 与相邻从设备互连的终端的位置在每个从设备中不同，从而在每个从设备中，从设备命令接收单元接收作为转接通线的结果具有修改值的标识命令，被连接在每个从设备中的不同位置。

9. 发明授权

US07346051B2 Slave device, master device and stacked device 有权
标题翻译：从设备，主设备和堆叠设备
公开(公告)号：US07346051B2
公开(公告)日：2008-03-18
申请号：US11149171
申请日：2005-06-10
申请人： Takeshi Nakayama , Eiji Takahashi , Yoshiyuki Saito , Yukihiro Ishimaru , Hideki Iwaki
发明人： Takeshi Nakayama , Eiji Takahashi , Yoshiyuki Saito , Yukihiro Ishimaru , Hideki Iwaki
IPC分类号： H04Q11/00 , H04L12/50 , H04L12/28 , H04L12/56 , H02J13/00 , G06F3/00 , G06F15/76
CPC分类号： G06F13/409 , G06F13/4226 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/16145 , H01L2924/00014 , H01L2224/05599 , H01L2224/05099
摘要： A stacked device is disclosed which is easily manufactured while identifying a plurality of devices that are stacked in the stacked device. The stacked device includes a stack of a plurality of slave devices and a master device having identical terminal arrangements. Here, the master device includes command transmission unit configured to input an identification command to a terminal of an adjacent slave device. Furthermore, the slave device includes a through-wire for interconnecting at least one terminal of that same device and an adjacent slave device; command reception unit configured to receive the identification command; and ID (identifier) setting unit configured to set the ID of that same device based on the identification command; the positions of the terminals that are interconnected with the adjacent slave devices differing in each slave device, so that, in each slave device, the slave device command reception unit receive an identification command having a modified value as a result of transiting through-wires that are connected at differing positions in each slave device.
摘要翻译：公开了一种容易制造的堆叠式装置，同时识别堆叠在堆叠装置中的多个装置。堆叠式装置包括多个从装置的堆叠和具有相同端子装置的主装置。这里，主设备包括命令传输单元，其被配置为向相邻从设备的终端输入识别命令。此外，从设备包括用于互连同一设备的至少一个终端和相邻从设备的通线; 命令接收单元，被配置为接收所述识别命令; ID（识别符）设定部，其基于所述识别命令来设定同一设备的ID; 与相邻从设备互连的终端的位置在每个从设备中不同，从而在每个从设备中，从设备命令接收单元接收作为转接通线的结果具有修改值的标识命令，被连接在每个从设备中的不同位置。

10. 发明授权

US08119919B2 Printed wiring board, method for manufacturing printed wiring board, and electric device 有权
标题翻译：印刷电路板，印刷电路板的制造方法以及电气装置
公开(公告)号：US08119919B2
公开(公告)日：2012-02-21
申请号：US12376862
申请日：2007-10-22
申请人： Hiroyoshi Tagi , Eiji Takahashi , Yoshiyuki Saito
发明人： Hiroyoshi Tagi , Eiji Takahashi , Yoshiyuki Saito
IPC分类号： H05K1/00
CPC分类号： H05K1/0228 , H05K1/0245 , H05K1/0393 , H05K3/4614 , H05K3/4635 , H05K2201/055 , H05K2201/097 , Y10T29/49128
摘要： Provided are a printed wiring board and a flexible printed wiring board which hardly generate radiation electromagnetic noises and are not easily affected by external noises. First and second wave-shape wirings are provided between at least two insulation substrates stacked on each other. The first and the second wave-shape wirings three-dimensionally intersect with each other in a plane direction and a thickness direction of the insulating substrates. The first and second wave-shape wirings are electrically separated from each other by a resist layer provided between the insulating substrates.
摘要翻译：提供了几乎不产生辐射电磁噪声并且不容易受到外部噪声的影响的印刷线路板和柔性印刷线路板。在彼此堆叠的至少两个绝缘基板之间设置第一和第二波形布线。第一和第二波形布线在绝缘基板的平面方向和厚度方向上彼此三维地相交。第一和第二波形布线通过设置在绝缘基板之间的抗蚀剂层彼此电分离。

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