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1. 发明授权

US5165343A Printing plate and printing process 失效
标题翻译：印版和印刷工艺
公开(公告)号：US5165343A
公开(公告)日：1992-11-24
申请号：US606731
申请日：1990-10-31
申请人： Eiichi Inoue , Mitsuru Takeda , Hitoshi Fujii , Minoru Utsumi , Noritaka Egashira , Satoru Kuramochi
发明人： Eiichi Inoue , Mitsuru Takeda , Hitoshi Fujii , Minoru Utsumi , Noritaka Egashira , Satoru Kuramochi
IPC分类号： B41M1/06 , B41M1/08 , B41N1/00 , B41N1/14 , G03F7/075
CPC分类号： B41M1/08 , B41N1/003 , B41N1/14 , G03F7/0757 , Y10T428/24802
摘要： A printing plate including a printing plate member, an easily deformable elastic layer laminated on the printing plate member, a surface layer having a higher elasticity than that of the elastic layer, laminated on the elastic layer, and a printing surface layer formed on the surface layer. The printing surface layer has an image area having an affinity with an ink and a non-image area having an ink repellancy.
摘要翻译：一种印刷版，其包括印刷板构件，层压在印刷板构件上的容易变形的弹性层，层叠在弹性层上的具有比弹性层更高的弹性的表面层，以及形成在表面上的印刷表面层层。印刷表面层具有与油墨的亲和性和具有拒墨性的非图像区域的图像区域。

2. 发明授权

US08069560B2 Method of manufacturing multilayer wiring board 有权
标题翻译：多层布线板的制造方法
公开(公告)号：US08069560B2
公开(公告)日：2011-12-06
申请号：US12708280
申请日：2010-02-18
申请人： Toshiaki Mori , Kazunori Nakamura , Satoru Kuramochi , Miyuki Akazawa , Koichi Nakayama
发明人： Toshiaki Mori , Kazunori Nakamura , Satoru Kuramochi , Miyuki Akazawa , Koichi Nakayama
IPC分类号： H01K3/10
CPC分类号： H01L23/49827 , H01L23/49822 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0306 , H05K1/0366 , H05K1/162 , H05K3/0041 , H05K3/0044 , H05K3/388 , H05K3/4061 , H05K3/4069 , H05K3/4076 , H05K3/426 , H05K3/4605 , H05K2201/0195 , H05K2201/068 , H05K2201/09563 , H05K2201/09581 , H05K2201/09763 , H05K2201/09827 , H05K2203/025 , H05K2203/1338 , H05K2203/1581 , Y10T29/43 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/49153 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： A manufacturing method of a multilayer wiring board that includes a core board, a wiring layer, and an electrically insulating layer that are stacked on the core board. The manufacturing method forms a plurality of through holes in a core member, a thermal expansion coefficient of the core board being between 2 to 20 ppm, and the core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal. The through holes are made conductive by a conductive material, to electrically connect between the front and the back of the core board. A wiring layer and an electrically insulating layer are stacked on one surface of the core board to form a multilayer wiring layer. A capacitor is formed on the other surface of the core board.
摘要翻译：一种多层布线板的制造方法，其包括堆叠在芯板上的芯板，布线层和电绝缘层。制造方法在芯部件中形成多个通孔，芯板的热膨胀系数在2〜20ppm之间，并且选自硅，陶瓷，玻璃，玻璃 - 环氧复合材料和金属中的芯构件。通孔由导电材料制成导电，以电连接芯板的正面和背面。布线层和电绝缘层堆叠在芯板的一个表面上以形成多层布线层。电容器形成在芯板的另一个表面上。

3. 发明授权

US07772684B2 Electronic device and production method thereof 有权
标题翻译：电子装置及其制造方法
公开(公告)号：US07772684B2
公开(公告)日：2010-08-10
申请号：US10980307
申请日：2004-11-04
申请人： Satoru Kuramochi , Yoshitaka Fukuoka
发明人： Satoru Kuramochi , Yoshitaka Fukuoka
IPC分类号： H01L23/02
CPC分类号： H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/82 , H01L25/0657 , H01L2221/68345 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/32225 , H01L2224/73267 , H01L2224/82001 , H01L2224/92244 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H05K1/185 , H05K3/4602 , H01L2924/00 , H01L2224/83005
摘要： An object is to provide an electronic device of a multilayer structure with high density and high reliability that can be reduced in size while incorporating an electronic component therein, and further provide a production method for easily producing such an electronic device. An electronic device of the present invention includes wiring layers and electrically insulating layers stacked on a core board and establishes predetermined electrical conduction between the wiring layers through upper-lower side conducting vias provided in the electrically insulating layers. An electronic component incorporating layer formed by directly forming on a lower layer an insulating resin layer having a cutout portion for receiving an electronic component therein and upper-lower side conducting vias and by incorporating the electronic component in the cutout portion is provided at least between one of the wiring layers and one of the electrically insulating layers and/or between the core board and the electrically insulating layer. At least the uppermost-layer electronic component incorporating layer of electronic component incorporating layers has a metal frame body surrounding the electronic component and the upper-lower side conducting vias, and a metal cap having a flange portion fixed to the metal frame body of the uppermost-layer electronic component incorporating layer is provided.
摘要翻译：本发明的目的是提供一种具有高密度和高可靠性的多层结构的电子器件，其可以在将电子元件并入的同时减小其尺寸，并且还提供了容易地制造这种电子器件的制造方法。本发明的电子器件包括堆叠在芯板上的布线层和电绝缘层，并且通过设置在电绝缘层中的上下侧导电孔而在布线层之间建立预定的导电。一种电子部件结合层，其通过在下层直接形成具有用于接收电子部件的切口部分的绝缘树脂层和上下侧导电通孔以及通过将电子部件并入切口部而形成的至少一个的布线层和电绝缘层之一和/或芯板与电绝缘层之间。至少具有电子元件结合层的最上层电子部件具有围绕电子部件和上下侧导电通孔的金属框体，金属盖具有固定在最上层的金属框体上的凸缘部提供了层间电子元件结合层。

4. 发明授权

US07690109B2 Method of manufacturing a multilayer wiring board 有权
标题翻译：多层布线板的制造方法
公开(公告)号：US07690109B2
公开(公告)日：2010-04-06
申请号：US11410984
申请日：2006-04-26
申请人： Toshiaki Mori , Kazunori Nakamura , Satoru Kuramochi , Miyuki Akazawa , Koichi Nakayama
发明人： Toshiaki Mori , Kazunori Nakamura , Satoru Kuramochi , Miyuki Akazawa , Koichi Nakayama
IPC分类号： H01K3/10
CPC分类号： H01L23/49827 , H01L23/49822 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0306 , H05K1/0366 , H05K1/162 , H05K3/0041 , H05K3/0044 , H05K3/388 , H05K3/4061 , H05K3/4069 , H05K3/4076 , H05K3/426 , H05K3/4605 , H05K2201/0195 , H05K2201/068 , H05K2201/09563 , H05K2201/09581 , H05K2201/09763 , H05K2201/09827 , H05K2203/025 , H05K2203/1338 , H05K2203/1581 , Y10T29/43 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/49153 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.
摘要翻译：在层叠在所述芯板的一个表面上的芯板，布线层和电绝缘层的多层布线基板中，所述芯板的XY方向的热膨胀系数在2〜20ppm的范围内所述芯板的核心部件是选自硅，陶瓷，玻璃，玻璃 - 环氧复合材料和金属的核心部件，所述芯板设置有多个在正面和背面之间导电的通孔通过导电材料，并且在所述芯板的一个表面上设置电容器，其中所述电容器包括在所述通孔中作为导电材料的上电极和设置成经由电介质层面对所述上电极的下电极。

5. 发明申请

US20060185141A1 Multilayer wiring board and manufacture method thereof 有权
公开(公告)号：US20060185141A1
公开(公告)日：2006-08-24
申请号：US11410984
申请日：2006-04-26
申请人： Toshiaki Mori , Kazunori Nakamura , Satoru Kuramochi , Miyuki Akazawa , Koichi Nakayama
发明人： Toshiaki Mori , Kazunori Nakamura , Satoru Kuramochi , Miyuki Akazawa , Koichi Nakayama
IPC分类号： H01G7/00 , H01K3/10
CPC分类号： H01L23/49827 , H01L23/49822 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0306 , H05K1/0366 , H05K1/162 , H05K3/0041 , H05K3/0044 , H05K3/388 , H05K3/4061 , H05K3/4069 , H05K3/4076 , H05K3/426 , H05K3/4605 , H05K2201/0195 , H05K2201/068 , H05K2201/09563 , H05K2201/09581 , H05K2201/09763 , H05K2201/09827 , H05K2203/025 , H05K2203/1338 , H05K2203/1581 , Y10T29/43 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/49153 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.

6. 发明授权

US07011931B2 Electrode for plasma display panel and process for producing the same 失效
标题翻译：等离子体显示面板用电极及其制造方法
公开(公告)号：US07011931B2
公开(公告)日：2006-03-14
申请号：US09985107
申请日：2001-11-01
申请人： Sakurako Hatori , Yasunori Kurima , Nobuaki Kimura , Yozo Kosaka , Satoru Kuramochi
发明人： Sakurako Hatori , Yasunori Kurima , Nobuaki Kimura , Yozo Kosaka , Satoru Kuramochi
IPC分类号： G03F7/00 , G03F7/40
CPC分类号： H01J11/12 , G03F7/0047 , H01J9/02 , H01J9/14 , H01J11/24 , H01J2211/225 , H01J2211/444 , Y10S428/914 , Y10T428/31504
摘要： A process for forming an electrode pattern for a plasma display panel, the process including coating a photosensitive conductive paste on a film to form a pattern forming layer, laminating the film onto a substrate with the pattern forming layer facing the substrate, exposing the pattern forming layer from above the film through a mask, separating and removing the film and developing the pattern forming layer to remove unexposed areas, and firing the substrate to adhere the exposed areas of the pattern forming layer to the substrate, thus forming an electrode pattern thereon.
摘要翻译：一种用于形成等离子体显示面板的电极图案的方法，该方法包括在薄膜上涂敷感光性导电糊以形成图案形成层，将图案形成层与基板相对地层压到基板上，使图案形成通过掩模从膜上方分离并除去膜并显影图案形成层以去除未曝光区域，并且烧制基板以将图案形成层的暴露区域附着到基板上，从而在其上形成电极图案。

7. 发明授权

US06605814B1 Apparatus for curing resist 有权
标题翻译：抗蚀剂固化装置
公开(公告)号：US06605814B1
公开(公告)日：2003-08-12
申请号：US09743806
申请日：2001-01-22
申请人： Nozomu Tadika , Satoru Kuramochi , Yoshiki Mimura
发明人： Nozomu Tadika , Satoru Kuramochi , Yoshiki Mimura
IPC分类号： A61N500
CPC分类号： H01L21/67109 , H01L21/6838
摘要： A resist curing device including a workpiece stage with a plate adapted to support a silicon wafer laid thereupon, a workpiece retention device that vacuum adsorbs the silicon wafer laid upon the plate, a light source unit that provides ultraviolet irradiation to cure resist applied to the silicon wafer, and a workpiece temperature control device that heats and/or cools the silicon wafer supported on the plate, where the plate has an expansion coefficient substantially similar to that of the silicon wafer.
摘要翻译：一种抗蚀剂固化装置，包括具有适于支撑沉积在其上的硅晶片的板的工件台，真空吸附放置在板上的硅晶片的工件保持装置，提供紫外线照射以固化施加到硅上的抗蚀剂的光源单元晶片和工件温度控制装置，其加热和/或冷却支撑在板上的硅晶片，其中板具有与硅晶片的膨胀系数基本相似的膨胀系数。

8. 发明授权

US06333140B1 Electrode for plasma display panel and process for producing the same 失效
标题翻译：等离子体显示面板用电极及其制造方法
公开(公告)号：US06333140B1
公开(公告)日：2001-12-25
申请号：US09675056
申请日：2000-09-29
申请人： Sakurako Hatori , Yasunori Kurima , Nobuaki Kimura , Yozo Kosaka , Satoru Kuramochi
发明人： Sakurako Hatori , Yasunori Kurima , Nobuaki Kimura , Yozo Kosaka , Satoru Kuramochi
IPC分类号： G03F726
CPC分类号： H01J11/12 , G03F7/0047 , H01J9/02 , H01J9/14 , H01J11/24 , H01J2211/225 , H01J2211/444 , Y10S428/914 , Y10T428/31504
摘要： An electrode, for a plasma display panel, adapted for provision on a front or back plate of a plasma display panel, the electrode comprising a conductive paste.
摘要翻译：一种用于等离子体显示面板的电极，其适于在等离子体显示面板的前板或后板上提供，所述电极包括导电浆料。

9. 发明授权

US5909083A Process for producing plasma display panel 失效
标题翻译：制造等离子体显示面板的方法
公开(公告)号：US5909083A
公开(公告)日：1999-06-01
申请号：US801859
申请日：1997-02-18
申请人： Masaaki Asano , Satoru Kuramochi , Yozo Kosaka
发明人： Masaaki Asano , Satoru Kuramochi , Yozo Kosaka
IPC分类号： H01J9/18 , H01J9/24 , H01J17/49
CPC分类号： H01J9/242 , H01J9/185 , H01J2211/36
摘要： A process for producing a plasma display panel, involving the formation of a predetermined pattern for a plasma display panel, including an electrode pattern and a barrier for defining a discharge space, said process comprising the steps of:forming a predetermined pattern-forming material layer on a substrate;forming a mask pattern, comprising a main component of the material layer, on the pattern-forming material layer:etching the pattern-forming material layer with the mask pattern formed thereon, thereby patterning the pattern-forming material layer; andthen firing the pattern-forming material layer with the mask pattern provided thereon and the mask layer, thereby integrating the pattern-forming material layer and at least part of the mask layer with each other.
摘要翻译：一种用于制造等离子体显示面板的方法，包括形成用于等离子体显示面板的预定图案，包括用于限定放电空间的电极图案和屏障，所述方法包括以下步骤：形成预定图案形成材料层在基材上在所述图案形成材料层上形成包括所述材料层的主要成分的掩模图案：用形成在其上的掩模图案蚀刻所述图案形成材料层，从而对所述图案形成材料层进行图案化; 然后用设置在其上的掩模图案和掩模层烧制图案形成材料层，从而将图案形成材料层和掩模层的至少一部分彼此整合。

10. 发明授权

US08114714B2 Electronic device and production method thereof 有权
标题翻译：电子装置及其制造方法
公开(公告)号：US08114714B2
公开(公告)日：2012-02-14
申请号：US11837763
申请日：2007-08-13
申请人： Satoru Kuramochi , Yoshitaka Fukuoka
发明人： Satoru Kuramochi , Yoshitaka Fukuoka
IPC分类号： H01L21/82
CPC分类号： H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/82 , H01L25/0657 , H01L2221/68345 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/32225 , H01L2224/73267 , H01L2224/82001 , H01L2224/92244 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H05K1/185 , H05K3/4602 , H01L2924/00 , H01L2224/83005
摘要： An object is to provide an electronic device of a multilayer structure with high density and high reliability that can be reduced in size while incorporating an electronic component therein, and further provide a production method for easily producing such an electronic device. An electronic device of the present invention includes wiring layers and electrically insulating layers stacked on a core board and establishes predetermined electrical conduction between the wiring layers through upper-lower side conducting vias provided in the electrically insulating layers. An electronic component incorporating layer formed by directly forming a lower layer and insulating resin layer having a cutout portion for receiving an electronic component therein and upper-lower side conducting vias and by incorporating the electronic component in the cutout portion is provided at least between one of the wiring layers and one of the electrically insulating layers and/or between the core board and the electrically insulating layer. At least the uppermost-layer electronic component incorporating layer of electronic incorporating layers has a metal frame body surrounding the electronic component and the upper-lower side conducting vias, and a metal cap having a flange portion fixed to the metal frame body of the uppermost-layer electronic component incorporating layer is provided.
摘要翻译：本发明的目的是提供一种具有高密度和高可靠性的多层结构的电子器件，其可以在将电子元件并入的同时减小其尺寸，并且还提供了容易地制造这种电子器件的制造方法。本发明的电子器件包括堆叠在芯板上的布线层和电绝缘层，并且通过设置在电绝缘层中的上下侧导电孔而在布线层之间建立预定的导电。通过直接形成下层形成的电子部件结合层和具有用于接收电子部件的切口部分的绝缘树脂层和上下侧导电通孔以及通过将电子部件并入缺口部分而形成的电子部件结合层至少设置在布线层和电绝缘层之一和/或芯板与电绝缘层之间。至少具有电子结合层的最上层电子部件具有围绕电子部件和上下侧导电通孔的金属框体，金属盖具有固定在最上层的金属框体上的凸缘部，提供了层叠电子元件结合层。

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