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1. 发明授权

US5164943A Cyclic redundancy check circuit 失效
标题翻译：循环冗余检查电路
公开(公告)号：US5164943A
公开(公告)日：1992-11-17
申请号：US847357
申请日：1992-03-06
申请人： Edwin Z. DeSouza , Daniel J. Cimino , Ramin Shirani , Mark R. Waggoner
发明人： Edwin Z. DeSouza , Daniel J. Cimino , Ramin Shirani , Mark R. Waggoner
IPC分类号： G06F13/00 , G11C15/04 , H04L12/46 , H04L12/56
CPC分类号： H04L49/901 , G11C15/04 , H04L12/4625 , H04L45/7453 , H04L49/90 , H04L49/9057
摘要： A media access controller is provided by the present invention. A feature of the media access controller of the present invention is a content addressable memory architecture whereby address filtering is provided for filtering physical, group and broadcast addresses on an Ethernet network. Another feature of the present invention is an interface architecture capable of supporting external address filters which in turn are capable of supporting spanning tree and source routing algorithms. Still another feature of the present invention is a CRC checker having improved testability such that burdensome computations for input bit test patterns are no longer required. Still another feature of the present invention is a first-in, first-out memory register having validity bits associated with each stored data byte, such that data bytes may be indiscriminately stored, regardless of their validity, and invalid data bytes are discarded during retrieval of the stored data bytes.

2. 发明授权

US5245617A First-in, first-out memory circuit 失效
标题翻译：先进先出的存储电路
公开(公告)号：US5245617A
公开(公告)日：1993-09-14
申请号：US847952
申请日：1992-03-06
申请人： Edwin Z. DeSouza , Daniel J. Cimino , Ramin Shirani , Mark R. Waggoner
发明人： Edwin Z. DeSouza , Daniel J. Cimino , Ramin Shirani , Mark R. Waggoner
IPC分类号： G11C15/04 , H04L12/46 , H04L12/56
CPC分类号： H04L12/4625 , G11C15/04 , H04L45/7453 , H04L47/23 , H04L49/90 , H04L49/901
摘要： A media access controller is provided by the present invention. A feature of the media access controller of the present invention is a content addressable memory architecture whereby address filtering is provided for filtering physical, group and broadcast addresses on an Ethernet network. Another feature of the present invention is an interface architecture capable of supporting external address filters which in turn are capable of supporting spanning tree and source routing algorithms. Still another feature of the present invention is a CRC checker having improved testability such that burdensome computations for input bit test patterns are no longer required. Still another feature of the present invention is a first-in, first-out memory register having validity bits associated with each stored data byte, such that data bytes may be indiscriminately stored, regardless of their validity, and invalid data bytes are discarded during retrieval of the stored data bytes.
摘要翻译：本发明提供一种媒体存取控制器。本发明的媒体接入控制器的特征是内容可寻址存储器架构，其中提供了用于过滤以太网上的物理，组和广播地址的地址过滤。本发明的另一个特征是能够支持外部地址过滤器的接口架构，其又能够支持生成树和源路由算法。本发明的另一个特征是具有改进的可测性的CRC校验器，使得不再需要用于输入比特测试模式的繁重的计算。本发明的另一个特征是具有与每个存储的数据字节相关联的有效位的先进先出存储器寄存器，使得数据字节可以被不加选择地存储，而不管它们的有效性，并且无效数据字节在检索期间被丢弃的存储数据字节。

3. 发明授权

US5617534A Interface protocol for testing of a cache memory 失效
标题翻译：用于测试缓存的接口协议
公开(公告)号：US5617534A
公开(公告)日：1997-04-01
申请号：US582380
申请日：1996-01-11
申请人： Mark J. Balmer , Mark R. Waggoner
发明人： Mark J. Balmer , Mark R. Waggoner
IPC分类号： G06F11/22 , G11C29/08 , G06F11/00
CPC分类号： G06F11/22 , G11C29/08
摘要： A computer system includes a microprocessor and an external cache memory coupled to the microprocessor. The cache memory includes a memory array and an apparatus for initiating a routine to test the integrity of the memory array in response to a signal asserted by the microprocessor. The apparatus generates a two-bit status signal coupled to the microprocessor for communicating IDLE, ACTIVE, PASS and FAIL states of the test routine. The apparatus initiates the test routine a predetermined of number clock cycles after the assertion of the signal provided by the microprocessor.
摘要翻译：计算机系统包括微处理器和耦合到微处理器的外部高速缓冲存储器。高速缓冲存储器包括存储器阵列和用于响应于由微处理器断言的信号来启动用于测试存储器阵列的完整性的例程的装置。该装置产生耦合到微处理器的两位状态信号，用于传送测试例程的IDLE，ACTIVE，PASS和FAIL状态。在由微处理器提供的信号的断言之后，装置启动测试程序预定的数字时钟周期。

4. 发明授权

US5640509A Programmable built-in self-test function for an integrated circuit 失效
标题翻译：集成电路可编程的内置自检功能
公开(公告)号：US5640509A
公开(公告)日：1997-06-17
申请号：US538793
申请日：1995-10-03
申请人： Mark J. Balmer , Mark R. Waggoner
发明人： Mark J. Balmer , Mark R. Waggoner
IPC分类号： G11C29/36 , G11C29/50 , G06F11/00
CPC分类号： G11C29/50 , G11C15/00 , G11C29/36
摘要： A method and apparatus for providing programmable self-testing in a memory. Registers in the memory are programmed with a sequence of instructions for performing the self-test of the memory. The sequence of instructions is run to perform the self-test of the memory, and the results are checked. The memory includes a clock multiplier which allows the registers to be programmed at a first clock rate, then the memory is tested at a second clock rate which is faster than the first clock rate.
摘要翻译：一种用于在存储器中提供可编程自检的方法和装置。存储器中的寄存器用一系列指令进行编程，以执行存储器的自检。运行指令序列以执行存储器的自检，并检查结果。存储器包括时钟倍增器，其允许以第一时钟速率对寄存器进行编程，然后以比第一时钟速率更快的第二时钟速率测试存储器。

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