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1. 发明授权

US5044750A Method for checking lithography critical dimensions 失效
标题翻译：检查光刻关键尺寸的方法
公开(公告)号：US5044750A
公开(公告)日：1991-09-03
申请号：US566561
申请日：1990-08-13
申请人： Edward M. Shamble
发明人： Edward M. Shamble
IPC分类号： G01B11/02 , G01R31/316 , G03F7/20 , H01L21/68
CPC分类号： G03F7/70625 , G01B11/02 , G01R31/316 , G03F7/70633 , H01L21/682
摘要： A method for measuring the proper exposure and registration of layers of desired circuit features on an integrated circuit wafer. The process of making the integrated circuit feature is modified in three ways. First, a structure is added to the mask pattern for each layer, apart from the desired circuit feature and parallel with and abutting the previous layer structure, comprising a plurality of geometric patterns arranged in a progressively overlapping edge-to-edge orientation on the mask pattern. The progressive overlap is such that at one end of the structure there is a substantial separation between the opposing edges of the geometric patterns, in the middle of the structure the opposing edges of the geometric patterns meet, and at the other end of the structure there is a substantial overlap of the opposing edges of the geometric patterns. The non-opposing edges of the geometric patterns are offset relative to a reference pattern in the middle of the structure. Second, the degree of exposure of the structure on a photoresist layer is analyzed. The proper degree of exposure is obtained when the opposing edges of each geometric pattern meet in the middle of the structure, an underexposed or overexposed condition exists when the point at which the opposing edges meet has shifted from the middle of the structure. Third, the registration of succeeding layers of features is analyzed. Proper registration is obtained when the abutting, non-opposing edges of the parallel structures of each layer meet at the reference pattern.
摘要翻译：一种用于测量集成电路晶片上所需电路特征层的适当曝光和配准的方法。制作集成电路特性的过程有三种修改。首先，除了期望的电路特征之外，还将每个层的掩模图形添加到掩模图案中，并且与先前的层结构平行并邻接，包括在掩模上以逐渐重叠的边缘到边缘取向排列的多个几何图案模式。渐进的重叠使得在结构的一端，几何图案的相对边缘之间存在实质上的间隔，在结构的中间，几何图案的相对边缘相遇，并且在该结构的另一端是几何图案的相对边缘的实质重叠。几何图案的非相对边缘相对于结构中间的参考图案偏移。第二，分析光致抗蚀剂层上结构的曝光程度。当每个几何图形的相对边缘在结构的中间相遇时，获得适当的曝光程度，当相对边缘相交的点已经从结构的中间偏移时，存在曝光不足或曝光过度的情况。第三，分析后续层次特征的注册。当每个层的平行结构的邻接的非相对边缘在参考图案处相遇时，获得适当的配准。

2. 发明授权

US06518591B1 Contact monitor, method of forming same and method of analizing contact-, via- and/or trench-forming processes in an integrated circuit 失效
标题翻译：接触式监测器，其形成方法以及在集成电路中分析接触，通孔和/或沟槽形成工艺的方法
公开(公告)号：US06518591B1
公开(公告)日：2003-02-11
申请号：US09561293
申请日：2000-04-28
申请人： Edward M. Shamble , Thomas Boonstra , David J. Brownell , David A. Crow
发明人： Edward M. Shamble , Thomas Boonstra , David J. Brownell , David A. Crow
IPC分类号： H01L2358
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76805 , H01L21/76807 , H01L22/24
摘要： Methods for monitoring defects in a process for forming a contact hole, via or trench in a layer of a device in an integrated circuit includes the steps of forming a sacrificial topology on a substrate by duplicating at least a portion of a structure of the device while substituting a material substantially free of elemental silicon for any elemental silicon present in the device to be monitored, etching the sacrificial topology at least to the substrate, removing at least a portion of the sacrificial topology, and inspecting the substrate using a wafer surface inspection tool. The substituted material, such as a dielectric material, can be easily etched and removed from the substrate, as compared to polysilicon. The etching step preferably creates an indentation in the substrate that is readily detectable by the wafer surface inspection tool. The etching step is preferably a selective etching step, having a selectivity of at least 10:1. The actual devices are then formed using the same or substantially the same process parameters as were used in forming the sacrificial topology of the monitor according to the present invention, thus insuring that properly formed contact holes, vias and/or trenches will also be formed in the actual device or devices.
摘要翻译：用于在集成电路中的器件层中形成接触孔，通孔或沟槽的工艺中的缺陷监测的方法包括以下步骤：通过复制器件结构的至少一部分而在衬底上形成牺牲拓扑，同时将基本上不含元素硅的材料替换为要监测的器件中存在的任何元素硅，至少蚀刻牺牲拓扑至衬底，去除牺牲拓扑的至少一部分，并使用晶片表面检查工具检查衬底。与多晶硅相比，诸如介电材料的取代材料可以容易地从衬底中蚀刻和去除。蚀刻步骤优选地在衬底中产生可由晶片表面检查工具容易地检测到的凹陷。蚀刻步骤优选为具有至少10:1选择性的选择性蚀刻步骤。然后使用与形成根据本发明的监视器的牺牲拓扑结构相同或基本上相同的工艺参数形成实际装置，从而确保也将形成适当形成的接触孔，通路和/或沟槽实际的设备或设备。

3. 发明授权

US6121156A Contact monitor, method of forming same and method of analyzing contact-, via-and/or trench-forming processes in an integrated circuit 有权
标题翻译：接触式监测器，其形成方法以及在集成电路中分析接触式，通孔式和/或沟槽形成方法的方法
公开(公告)号：US6121156A
公开(公告)日：2000-09-19
申请号：US204215
申请日：1998-12-02
申请人： Edward M. Shamble , Thomas Boonstra , David J. Brownell , David A. Crow
发明人： Edward M. Shamble , Thomas Boonstra , David J. Brownell , David A. Crow
IPC分类号： H01L21/60 , H01L21/66 , H01L21/768 , H01L21/00
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76807 , H01L22/24
摘要： Methods for monitoring defects in a process for forming a contact hole, via or trench in a layer of a device in an integrated circuit includes the steps of forming a sacrificial topology on a substrate by duplicating at least a portion of a structure of the device while substituting a material substantially free of elemental silicon for any elemental silicon present in the device to be monitored, etching the sacrificial topology at least to the substrate, removing at least a portion of the sacrificial topology, and inspecting the substrate using a wafer surface inspection tool. The substituted material, such as a dielectric material, can be easily etched and removed from the substrate, as compared to polysilicon. The etching step preferably creates an indentation in the substrate that is readily detectable by the wafer surface inspection tool. The etching step is preferably a selective etching step, having a selectivity of at least 10:1. The actual devices are then formed using the same or substantially the same process parameters as were used in forming the sacrificial topology of the monitor according to the present invention, thus insuring that properly formed contact holes, vias and/or trenches will also be formed in the actual device or devices.
摘要翻译：用于在集成电路中的器件层中形成接触孔，通孔或沟槽的工艺中的缺陷监测的方法包括以下步骤：通过复制器件结构的至少一部分而在衬底上形成牺牲拓扑，同时将基本上不含元素硅的材料替换为要监测的器件中存在的任何元素硅，至少蚀刻牺牲拓扑至衬底，去除牺牲拓扑的至少一部分，并使用晶片表面检查工具检查衬底。与多晶硅相比，诸如介电材料的取代材料可以容易地从衬底中蚀刻和去除。蚀刻步骤优选地在衬底中产生可由晶片表面检查工具容易地检测到的凹陷。蚀刻步骤优选为具有至少10:1选择性的选择性蚀刻步骤。然后使用与形成根据本发明的监视器的牺牲拓扑结构相同或基本上相同的工艺参数形成实际装置，从而确保也将形成适当形成的接触孔，通路和/或沟槽实际的设备或设备。

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